Fast floorplanning for effective prediction and construction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 2, 2001, Pages 341-350

  Ranjan, Abhishek ^b   Bazargan, Kiarash ^c   Ogrenci, Seda ^d   Sarrafzadeh, Majid ^a,d  

^a IEEE   (United States)

^b Monterey Design Systems   (United States)

^c UNIVERSITY OF MINNESOTA   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Construction; Floorplanning; Prediction

Indexed keywords

ALGORITHMIC PREDICTOR; CONSTRUCTIVE PREDICTION; FLOORPLANNING PROBLEM; SOFTWARE PACKAGE TIMBERWOLF1.4.0;

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SIMULATED ANNEALING; THEOREM PROVING; VLSI CIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 0035301378     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.924056     Document Type: Article

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