PMP: Performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 428-431

  Hwang, Chanseok ^a   Pedram, Massoud ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COARSENING AND REFINEMENTS; CONNECTION STRENGTH; HOPCOUNT; MULTI-LEVEL PARTITIONING; MULTI-LEVEL PARTITIONING ALGORITHM; MULTILEVEL CLUSTERING; PARTITIONING STRATEGIES; PERFORMANCE-DRIVEN; PRIMARY OBJECTIVE; SIGNAL DIRECTION; THREE PHASIS;

CLUSTERING ALGORITHMS;

COMPUTER AIDED DESIGN;

EID: 33748583962     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, Multilevel Hypergraph Partitioning. Application in VLSl Domain. In ACM/IEEE DAC, 526-529. 1997.
2. C. I. Alpert, I. H. Huang and A. B. Kahng, Multilevel Circuit Partitioning. In ACMIEEE DAC, 530-533, 1997.
3. J. Cong, H. P. Hi, S. K. Lim, T. Shibuya and D. Xu, Luge Scale Circuit Partitioning with LoosdStable Net Removal and Signal Flow Based Clustering. In IEEE ICCD, 444-446, 1997.
4. J. Cong and S.K. Lim, Performance Driven Multiway Partitioning. In ACM/IEEE ASP-DAC, 441-446, 2000.
5. A. B. Kahng and X. Xu, Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in Pedormance-driven bipartitioning. In ACWIEEE ISPD, 81-86,2003
6. J. Cong, S. Lim and C. Wu, Perfomance Driven Multi-level and Multiway Partitioning with Retiming. In ACM/IEEE DAC, 274-279, 2000.
7. I. Cong and C. Wu. Global Clustering-Based Performance Driven Circuit Partitioning. InACM/IEEEZSPD, 149-154,2002.
8. J. Cong. H. Li and C. Wu, Simultaneous Circuit PartitioinglClustemg with Retiming for Performance Optimization. In ACM/IEEE DAC, 460-465, 1999.
9. C. Ababei, S. Navaratnasothie, K. Bazargan and G. Karypis, Multiobjective Circuit Partitioning for Cursize and Path-Based Dela/ Minimization. In IEEE ICCAD, 181-185, 2002.
10. C. Ababei and K. Bazargan, Statistical Timing Driven Partitioning far VLSI Circuits. In DATE, 1109,2002.
11. Shihliang Ou and Massoud Pedram, Timing-driven bipartitioning with replication using iterative quadratic programming. In ACMMEEE ASP-DAC, 105-108, 1999.
12. C. Fiduccia and R. Mattheyses, A Linear Time Heuristic for Improving Network Partitions. In ACM/IEEE DAC, 175-181, 1988.
13. A. E. Caldwell, A. B. Kahng, I. L. Markov, Hypergrdph Partitioning with Fixed Vertices. In ACM/IEEE DAC, 355-359, 1999.
14. G. Karypis and V. Kumar. hMetis 1.5: A Hypergraph Partitioning Package. Technical repot, Department of Computer Science, Univ. of Minnesota. 1998.
15. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H Savoj, P.R. Stephan, R.K. Bray" A. Sangiovanni-Vincentelli, 'SIS: A System for Sequential Circuit Synthesis', Technical Report UCBERL M92/41, Univ. of Califomia, Berkeley, May 1992.