Multi-objective circuit partitioning for cutsize and path-based delay minimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 181-185

  Ababei, Cristinel ^a   Navaratnasothie, Selvakkumaran ^b   Bazargan, Kia ^a   Karypis, George ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAY MINIMIZATION; ELMORE DELAY; MULTI-OBJECTIVE PARTITIONING METHOD; TIMING DRIVEN PLACEMENT ALGORITHM;

ALGORITHMS; COMPUTER SIMULATION; DELAY CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036911943     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774599     Document Type: Conference Paper

References (12)

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