Incremental Placement for Timing Optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 463-466

  Choi, Wonjoon ^a   Bazargan, Kia ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; LINEAR PROGRAMMING; OPTIMIZATION; PERTURBATION TECHNIQUES; PROBLEM SOLVING; TIMING CIRCUITS;

NET CONSTRAINT GENERATION; TIMING DRIVEN PLACEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0348040118     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H. Eisenmann and F. M. Johannes, "Generic Global Placement and Floorplanning", ACM/IEEE Design Automation Conference, 1998.
2. B. Halpin, C. Y. roger Chen, and Naresh Sehgal, "Timing Driven Placement using Physical Net Constraints", Design Automation Conference, pp.780-783. IEEE/ACM, June 2001.
3. K. Rajagopal et al., "Timing Driven Force Directed placement with Physical Net Constraints", International Symposium on Physical Design, pp 60-66. IEEE/ACM, April 2003.
4. A. H. Ajami and M. Pedram, "Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with Movable Steiner Points", ASPDAC, 2001
5. ftp://ftp.es.ele.tue.nl/pub/lp_solve/. Information and Communication Systems group at the Electrical Engineering department of the Eindhoven University of Technology, 1998.
6. http://www.cs.wisc.edu/̃swright/ooqp/. University of Chicago, 2001
7. C. Ababei, N. Selvakkumaran, K. Bazargan, and G. Karypis, "Multi-objective Circuit Partitioning for Cutsize and Path-based Delay Minimization," ICCAD, 2002
8. X. Yang, B.K. Choi, and M. Sarrafzadeh, "Timing-Driven Placement using Design Hierarchy Guided Constraint Generation", ICCAD, 2002.