Modeling repeaters explicitly within analytical placement

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 699-704

  Saxena, Prashant ^a   Halpin, Bill ^b  

^a INTEL CORPORATION   (United States)

^b Synplicity Inc   (United States)

Author keywords

Analytical placement; Buffering; Force directed placement; Interconnect; Placement; Repeater insertion; Scaling

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; LAWS AND LEGISLATION; LOGIC PROGRAMMING; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING;

ANALYTICAL PLACEMENT; BUFFERING; FORCE-DIRECTED PLACEMENT; INTERCONNECTS; PLACEMENT; REPEATER INSERTION; SCALING;

TELECOMMUNICATION REPEATERS;

EID: 4444339015     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996759     Document Type: Conference Paper

References (11)

1. Alpert, C.J., Gandham, G., Hrkic, M., Hu, J., and Quay, S.T., Porosity aware buffered steiner tree construction. Int. Symp. Physical Design, 2003, 158-165.
2. Changfan, C., Hsu, Y.-C., and Tsai, F.-S. Timing Optimization on Routed Designs with Incremental Placement and Routing Characterization. IEEE Trans. CAD, 19, 2 (Feb. 2000), 188-196.
3. Cong, J., Kong, T., and Pan, D.Z. Buffer block planning for interconnect-driven floorplanning. Int. Conf. Computer-aided Design, 1999, 358-363.
4. Davis, J.A., De, V.K., and Meindl, J.D. A Stochastic Wire-length Distribution for Gigascale Integration (GSI). IEEE Trans. Electron Devices, 45, 3 (Mar. 1998), 580-597.
5. Eisenmann, H., and Johannes, F.M. Generic Global Placement and Floorplanning. Design Automation Conf, 1998, 269-274.
6. Kleinhans, J.M., Sigl, G., Johannes, P.M., and Antreich, K. GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization. IEEE Trans. CAD, 10, 3 (Mar. 1991), 356-365.
7. Rajagopal, K., Shaked, T., Parasuram, Y., Cao, T., Chowdhary, A., and Halpin, B. Timing Driven Force Directed Placement with Physical Net Constraints. Int. Symp. Physical Design, 2003, 60-66.
8. Saxena, P., Menezes, N., Cocchini, P., and Kirkpatrick, D.A. Repeater Scaling and its Impact on CAD. IEEE Trans. CAD, 23, 4 (Apr. 2004).
9. Sigl, G., Doll, K., and Johannes, F.M. Analytical Placement: A Linear or a Quadratic Objective Function? Design Automation Conf., 1991, 427-432.
10. Stenz, G., Riess, B.M., Rohfleisch, B., and Johannes, F.M. Performance Optimization by Interacting Netlist Transformations and Placement. IEEE Trans. CAD, 19, 3 (Mar. 2000), 350-358.
11. Villarrubia, P. Important Placement Considerations for Modern VLSI Chips. Invited talk, Int. Symp. Physical Design, 2003.