FastPlace 2.0: An efficient analytical placer for mixed-mode designs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 195-200

  Viswanathan, Natarajan ^a   Pan, Min ^a   Chu, Chris ^a  

^a Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MACROS; OPTIMIZATION; PERTURBATION TECHNIQUES; PROBLEM SOLVING;

ACADEMIC PLACER CAPO 9.1; MACRO LEGALIZATION ALGORITHMS; MIXED-MODE DESIGNS; WIRELENGTHS;

INTEGRATED CIRCUIT LAYOUT;

EID: 33748618422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Standard performance evaluation corporation. http://www.spec. org/.
2. S. N. Adya, S. Chaturvedi, J. A. Roy, D. Papa, and I. L. Markov. Unification of partitioning, floorplanning and placement. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 550-557, 2004.
3. S. N. Adya and I. L. Markov. ISPD02 IBM-MS Mixed-size Placement Benchmarks. http://vlsicad.eecs.umich.edu/BK/ISPD02bench/.
4. S. N. Adya and I. L. Markov. Consistent placement of macro-blocks using floorplanning and standard-cell placement. In Proc. Intl. Symp. on Physical Design, pages 12-17, 2002.
5. S. N. Adya and I. L. Markov. Combinatorial techniques for mixed-size placement. ACM Trans. Design Automation of Electronics Systems, 10(1):58-90, January 2005.
6. U. Brenner and M. Struzyna. Faster and better global placement by a new transportation algorithm. In Proc. ACM/IEEE Design Automation Conf., pages 591-596, 2005.
7. C. C. Chang, J. Cong, and X. Yuan. Multi-level placement for large-scale mixed-size IC designs. In Proc. Asia and South Pacific Design Automation Conf., pages 325-330, 2003.
8. H. Eisenmann and F. Johannes. Generic global placement and floorplanning. In Proc. ACM/IEEE Design Automation Conf., pages 269-274, 1998.
9. S. Goto. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. Circuits and Systems, CAS-28(1):12-18, 1981.
10. A. B. Kahng and Q. Wang. An analytical placer for mixed-size placement and timing-driven placement. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 565-572, 2004.
11. A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, and P. H. Madden. Recursive bisection based mixed block placement. In Proc. Intl. Symp. on Physical Design, pages 84-89, 2004.
12. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. VLSI module placement based on rectangle-packing by the sequence pair. IEEE Trans. Computer-Aided Design, 15(12):1518-1524, December 1996.
13. M. Pan, N. Viswanathan, and C. Chu. An efficient and effective detailed placement algorithm. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 48-55, 2005.
14. N. Viswanathan and C. C.-N. Chu. ISPD04 IBM Standard Cell Benchmarks with Pads. http://www.public.iastate.edu/~ nataraj/ISPD04_Bench.html.
15. N. Viswanathan and C. C.-N. Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. Intl. Symp. on Physical Design, pages 26-33, 2004.
16. K. Vorwerk and A. Kennings. An improved multi-level framework for force-directed placement. In Proc. Conf. on Design Automation and Test in Europe, pages 902-907, 2005.
17. K. Vorwerk, A. Kennings, and A. Vannelli. Engineering details of a stable force-directed placer. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 573-580, 2004.
18. B. Yao, H. Chen, C.-K. Cheng, N.-C. Chou, L.-T. Liu, and P. Suaris. Unified quadratic programming approach for mixed mode placement. In Proc. Intl. Symp. on Physical Design, pages 193-199, 2005.
19. H. Yu, X. Hong, and Y. Cai. MMP: A novel placement algorithm for combined macro block and standard cell layout design. In Proc. Asia and South Pacific Design Automation Conf., pages 271-276, 2000.