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Volumn 50, Issue 4-5, 2006, Pages 451-468

Product-representative "at speed" test structures for CMOS characterization

Author keywords

[No Author keywords available]

Indexed keywords

BUSINESS MACHINES; DATA REDUCTION; DATA STRUCTURES; MICROPROCESSOR CHIPS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

EID: 33748566775     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.504.0451     Document Type: Article
Times cited : (34)

References (21)
  • 1
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    • "A Ring Oscillator Based Variation Test Chip"
    • M. Eng. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, May
    • J. S. Panganiban, "A Ring Oscillator Based Variation Test Chip," M. Eng. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, May 2002.
    • (2002)
    • Panganiban, J.S.1
  • 2
    • 0031077147 scopus 로고    scopus 로고
    • "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices"
    • B. E. Stine, E. Chang, D. S. Boning, and J. E. Chung, "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices," IEEE Trans. Semicond. Manuf. 10, 24-41 (1997).
    • (1997) IEEE Trans. Semicond. Manuf. , vol.10 , pp. 24-41
    • Stine, B.E.1    Chang, E.2    Boning, D.S.3    Chung, J.E.4
  • 8
    • 24144444103 scopus 로고    scopus 로고
    • "Photon Emission Microscopy of Inter/Intra Chip, Device Performance Variations"
    • S. Polonsky, M. Bhushan, A. Gattiker, A. Weger, and P. Song, "Photon Emission Microscopy of Inter/Intra Chip, Device Performance Variations," Microelectron. Reliabil. 45, 1471-1475 (2005).
    • (2005) Microelectron. Reliabil. , vol.45 , pp. 1471-1475
    • Polonsky, S.1    Bhushan, M.2    Gattiker, A.3    Weger, A.4    Song, P.5
  • 9
    • 0041340533 scopus 로고    scopus 로고
    • "Negative Bias Temperature Instability: A Road to Cross in Deep Submicron CMOS Manufacturing"
    • D. K. Schroder and J. A. Babcock, "Negative Bias Temperature Instability: A Road to Cross in Deep Submicron CMOS Manufacturing," J. Appl. Phys. 94, 1-18 (2003).
    • (2003) J. Appl. Phys. , vol.94 , pp. 1-18
    • Schroder, D.K.1    Babcock, J.A.2
  • 10
    • 0042912833 scopus 로고    scopus 로고
    • "Simulations and Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETS"
    • A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulations and Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETS," IEEE Trans. Electron Devices 50, 1838 (2003).
    • (2003) IEEE Trans. Electron Devices , vol.50 , pp. 1838
    • Asenov, A.1    Brown, A.R.2    Davies, J.H.3    Kaya, S.4    Slavcheva, G.5
  • 12
    • 0036714040 scopus 로고    scopus 로고
    • "Electrically Programmable Fuse (eFuse) Using Electromigration in Silicides"
    • C. Kothandaraman, S. K. Iyer, and S. S. Iyer, "Electrically Programmable Fuse (eFuse) Using Electromigration in Silicides," IEEE Electron Device Lett. 23, 523-525 (2002).
    • (2002) IEEE Electron Device Lett. , vol.23 , pp. 523-525
    • Kothandaraman, C.1    Iyer, S.K.2    Iyer, S.S.3
  • 13
    • 33748528704 scopus 로고    scopus 로고
    • "Method and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit"
    • U.S. Patent filed (IBM Docket No. YOR920040458US1)
    • M. Bhushan, K. Chandrasekara, M. Ketchen, and E. Maciejewski, "Method and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit," U.S. Patent filed (IBM Docket No. YOR920040458US1), 2005.
    • (2005)
    • Bhushan, M.1    Chandrasekara, K.2    Ketchen, M.3    Maciejewski, E.4
  • 15
    • 1942455774 scopus 로고    scopus 로고
    • "Time-Resolved Measurements of Self-Heating in SOI and Strained Silicon MOSFETs Using Photon Emission Microscopy"
    • S. Polonsky and K. A. Jenkins, "Time-Resolved Measurements of Self-Heating in SOI and Strained Silicon MOSFETs Using Photon Emission Microscopy," IEEE Electron Device Lett. 25, 208-210 (2004).
    • (2004) IEEE Electron Device Lett. , vol.25 , pp. 208-210
    • Polonsky, S.1    Jenkins, K.A.2
  • 18
    • 16244421355 scopus 로고    scopus 로고
    • "Technique for Rapid, In-Line Characterization of Switching History in Partially Depleted SOI Technologies"
    • D. J. Pearson, M. B. Ketchen, and M. Bhushan, "Technique for Rapid, In-Line Characterization of Switching History in Partially Depleted SOI Technologies," Proceedings of the IEEE International SOI Conference, 2004, pp. 148-150.
    • (2004) Proceedings of the IEEE International SOI Conference , pp. 148-150
    • Pearson, D.J.1    Ketchen, M.B.2    Bhushan, M.3
  • 19
    • 1842427538 scopus 로고    scopus 로고
    • "Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates"
    • M. B. Ketchen, M. Bhushan, and C. J. Anderson, "Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates," Rev. Sci. Instrum. 75, 768-771 (2004).
    • (2004) Rev. Sci. Instrum. , vol.75 , pp. 768-771
    • Ketchen, M.B.1    Bhushan, M.2    Anderson, C.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.