High speed test structures for in-line process monitoring and model calibration

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 33-38

  Ketchen, Mark ^a   Bhushan, Manjul ^b   Pearson, Dale ^a  

^a IBM RESEARCH   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; SWITCHING;

CMOS GATES; LEAKAGE COMPONENTS; RING OSCILLATORS;

PROCESS ENGINEERING;

EID: 27644574245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Yuan Taur and Tak H. Ning. Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, UK 1998.
2. Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Pub. Company, New York, 1992.
3. M. B. Ketchen, M. Bhushan, and C. J. Anderson, "Circuit and Technique for Characterizing Switching Delay History Effects in Silicon-On-Insulator Logic Gates", RSI, 75, pp. 768-771 2004.
4. S. Fung, et. al. "Controlling Floating-Body Effects for 0.13 μm and 0.10 μm SOI CMOS," IEDM 2000 Technical Digest, p. 231.
5. D. J. Pearson, M. B. Ketchen and M. Bhushan, 'Technique for Rapid, In-Line Characterization of Switching History in Partially Depleted SOI Technologies", Proc. of 2004 SOI Conference, pp. 148-150, 2004.
6. S. Kawanaka et al. "Body Voltage and History Effect Sensitivity to Key Device Parameters in 90nm PD SOI", Proc. of 2004 SOI Conference, pp. 19-20, 2004.