Technique for rapid, in-line characterization of switching history in partially depleted SOI technologies

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 148-150

  Pearson, Dale J ^a   Ketchen, Mark B ^a   Bhushan, Manjul ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CHAIN TECHNIQUE; GATE DELAYS; IN-LINE PARAMETRIC TESTERS; PULSE FORMATION;

AUTOMATION; ELECTRIC NETWORK ANALYSIS; ELECTROMAGNETIC WAVE PROPAGATION; FEEDBACK; FUNCTIONS; GATES (TRANSISTOR); MULTIPLEXING; SWITCHING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 16244421355     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Fung, et al., "Controlling Floating-Body Effects for 0.13 μm and 0.10 μm SOI CMOS," IEDM 2000 Technical Digest, p231.
2. S. Mathew, et. al., "Sub-500 p-sec 64b ALUs in 0.18 μm SOI/Bulk CMOS: Design and Scaling Trends," Digest of the 2001 ISSCC, p. 318.
3. M. B. Ketchen, et. al., "Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates," Rev. of Scientific Inst., in press