Challenges in the formal verification of complete state-of-the-art processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 603-606

  Ayewah, Nathaniel ^a   Kikkeri, Nikhil ^a   Seidel, Peter Michael ^a   Beyer, Sven ^b  

^a Southern Methodist University   (United States)

^b OneSpin Solutions   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN COMPLEXITIES; HARDWARE VERIFICATION; INTUITIVE INTERFACE; PROCESSOR DESIGNS;

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; INTERFACES (COMPUTER); PROBLEM SOLVING; PRODUCTIVITY;

PROGRAM PROCESSORS;

EID: 33748533153     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.37     Document Type: Conference Paper

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