Comparative study of strategies for formal verification of high-level processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 119-124

  Velev, Miroslav N ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FORMULAS; POSITIVE EQUALITY; PROPOSITIONAL LOGIC; UNITERPRETED FUNCTION (UF);

BOOLEAN FUNCTIONS; COMPUTER SYSTEMS; ENCODING (SYMBOLS); MATHEMATICAL MODELS; SYNTACTICS; TREES (MATHEMATICS);

MICROPROCESSOR CHIPS;

EID: 17644416138     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347910     Document Type: Conference Paper

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