Sizing CMOS circuits for increased transient error tolerance

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 11-16

  Dhillon, Yuvraj S ^a   Diril, Abdulkadir U ^a   Chatterjee, Abhijit ^a   Singh, Adit D ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSIENT ERROR PROPAGATION; TRANSIENT ERROR TOLERANCE; VOLTAGE AMPLITUDE; VOLTAGE WAVEFORMS;

ALGORITHMS; CAPACITANCE; COMBINATORIAL CIRCUITS; ERROR ANALYSIS; ITERATIVE METHODS; LOGIC GATES; MATHEMATICAL MODELS; MICROELECTRONICS; VECTORS; VOLTAGE MEASUREMENT; WAVEFORM ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 10444278059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319653     Document Type: Conference Paper

References (8)

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