Circuit techniques in a 266-MHz MMX-enabled processor

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1650-1662

  Draper, Don ^{a,b,e,f,g,h,i,j}   Crowley, Matt ^a,b,k,l   Holst, John ^a,b,m,n,o,p   Favor, Greg ^b,j,q   Schoy, Albrecht ^b   Trull, Jeff ^b   Ben Meir, Amos ^b   Khanna, Rajesh ^b   Wendell, Dennis ^a,b   Krishna, Ravi ^b   Nolan, Joe ^a,b   Mallick, Dhiraj ^b   Partovi, Hamid ^a,b   Roberts, Mark ^a,b   Johnson, Mark ^a,b,c   Lee, Thomas ^a,b,d  

^a IEEE   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c Transmeta Corporation   (United States)

^d STANFORD UNIVERSITY   (United States)

^e UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^f CARLETON UNIVERSITY   (Canada)

^g NORTEL NETWORKS   (Canada)

^h American Microsystems   (United States)

ⁱ Fairchild Intergraph Adv Proc Div   (United States)

^j NexGen ^*

^k UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^l Amdahl Corporation   (United States)

^m UNIVERSITY OF IOWA   (United States)

ⁿ STMICROELECTRONICS   (Italy)

^o Unisys   (United States)

^p Intergraph Corporation   (United States)

^q CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

more..

Author keywords

Cache memories; Computer architecture; Design automation software; Flip flops; Integrated circuit design; Logic design; Phase locked loops; Programmable logic array; Read only memories

Indexed keywords

BUFFER STORAGE; COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; FLIP CHIP DEVICES; FLIP FLOP CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; PROGRAMMABLE LOGIC CONTROLLERS; ROM;

CERAMIC PIN GRID ARRAY; DESIGN AUTOMATION SOFTWARE; MMX ENABLED PROCESSOR; SUPERSCALAR EXECUTION ENGINE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031271850     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641685     Document Type: Article

References (15)

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