Extraction Error Diagnosis and Correction in High-Performance Designs

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 423-430

  Yang, Yu Shen ^a   Brandon Liu, J ^a   Thadikaran, Paul ^b   Veneris, Andreas ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; LOGIC GATES;

LOGIC EXTRACTION;

VLSI CIRCUITS;

EID: 0142184807     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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