Extraction error modeling and automated model debugging in high-performance low power custom designs

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 996-1001

  Yang, Yu Shen ^a   Veneris, Andreas ^a   Thadikaran, Paul ^b   Venkataraman, Srikanth ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED DEBUGGING; AUTOMATED MODELS; SEMI-AUTOMATED PROCESS;

COMPUTER ARCHITECTURE; ERROR ANALYSIS; FORMAL LOGIC; MATHEMATICAL MODELS; PROBLEM SOLVING; PROGRAM DEBUGGING;

SYSTEMS ANALYSIS;

EID: 33646926963     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.151     Document Type: Conference Paper

References (10)

1. M. Abadir, J. Ferguson, and T. Kirkland. Logic verification via test generation. IEEE Trans. CAD, 7:138-148, January 1988.
2. H. Ando, Y. Yoshida, A. Inoue, I. Sugiyamal, T. Asakawa, K. Morita, T. Muta, T. Motokurumada, S. Okada, H. Yamashita, Y. Satsukawa, A. Konmoto, R. Yamashita, and H. Sugivama. A 1.3-ghz fifth-generation sparc64 micrprocessor. IEEE Journal of Solid-State Circuits, 38(11):1896-1905, 2003.
3. D. Bearden, D. Caffo, P. Anderson, P. Rossbach, N. Iyengar, T. Petrsen, and J.-T. Yen. A 780mhz powerpc microprocessor with integrated 12 cache. IEEE ISSCC, pages 90-91, 2000.
4. S. Kundu. GateMaker: A Transistor to Gate Level Model Extraction for Simulation, Automatic Test Pattern Generation and Verification. IEEE ITC, pages 372-381, 1998.
5. N. Kurd, J. Barkatullah, R. Dizon, and T. Fletcher. A multi-gigahert clocking scheme for the pentium® 4 microprocessor. IEEE Journal of Solid-State Circuits, 36(11):1647-1653, Nov. 2001.
6. M. Kusko, B. Robbins, T. Snethen, P. Song, T. Foote, and W. Huott. Microprocessor test and test tool methodology for the 500mhz ibm s/390 g5 chip. Proc. IEEE ITC, 1998.
7. J. Liu, A. Veneris, and H. Takahashi, Incremental diagnosis of multiple open-interconnects. Proc. IEEE ITC, pages 1085-1092, 2002.
8. A. Veneris and I. Hajj. Design error diagnosis and correction via test vector simulation. IEEE Trans. CAD. 18(12):1803-1816, December 1999.
9. S. Venkataraman and W. Fuchs. A deductive technique for diagnosis of bridging faults. Proc. IEEE ICCAD, pages 562-567, 1997.
10. Y. Yang, J. Liu, P. Thadikaran, and A. Veneris. Extraction error diagnosis and correction in high-performance designs. Proc. IEEE ITC, pages 423-430, 2003.