An automated method for test model generation from switch level circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 769-774

  McDougall, T ^a   Parashkevov, A ^a   Jolly, S ^b   Zhu, Juhong ^a   Zeng, Jing ^a   Pyron, C ^a   Abadir, M ^a  

^a MOTOROLA INC   (United States)

^b FourSticks Pty Ltd   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTER AIDED DESIGN; RECONFIGURABLE HARDWARE; VLSI CIRCUITS;

AUTOMATED FLOW; AUTOMATED METHODS; ERROR-PRONE PROCESS; GATE LEVELS; LEVEL OF ABSTRACTION; OPERATING REQUIREMENTS; TEST MODELING; TEST MODELS;

DESIGN FOR TESTABILITY;

EID: 33746929799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195123     Document Type: Conference Paper

References (8)

1. Groupe Bull, "Generalized Recognition of Gates: User's Guide", Version 06, April 4 1996.
2. Motorola Semiconductor Israel Limited, "The MatchMaker Tool User Guide", Motorola Internal Document, June 1997.
3. R.E. Bryant, "Boolean Analysis of MOS Circuits", IEEE Transactions on CAD, vol. 6, no. 4, pp. 634-649, July 1987.
4. R.E. Bryant, "Extraction of Gate-Level Models from Transistor Circuits by Four-Valued Symbolic Analysis", IEEE ICCAD'91.
5. COMPASS Design Automation, "Laybool User Guide", Beta Test Edition, April 1997.
6. A. Gavrilov, S. Gavrilov, D. Blaauw, G. Vijayan, S. Pullela, and S. Moore, "Resynthesis of Static CMOS Circuits for Low Power", Motorola Internal Document, 1997.
7. S. Kundu, "GateMaker: A Transistor to Gate Level Model Extractor for Simulation, Automatic Test Pattern Generation and Verification", IEEE International Test Conference, pp. 372-381, 1998.
8. S. Jolly, A. Parashkevov, T. McDougall, "SLV: A Tool for Equivalence Checking of Custom Circuits at the Switch Level", IEEE Design Automation Conference, pp. 299-304, June 2002