A four channel, self-calibrating, high resolution, time to digital converter

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 1998, Pages 409-412

  Mota, M ^a,b   Christiansen, J ^b  

^a LIP   (Portugal)

^b CERN   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; PHASE LOCKED LOOPS; SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; ERROR ANALYSIS;

CMOS PROCESSS; DELAY-LOCKED LOOPS; HIGH RESOLUTION; ITS ARCHITECTURE; REFERENCE CLOCK; SELF-CALIBRATING; TIME COUNTERS; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS; ELECTRIC CONVERTERS;

HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTERS (HRTDC);

EID: 0032282803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.813351     Document Type: Conference Paper

References (7)

1. O. Sasaki et al., "A high resolution TDC in TKO BOX system", IEEE Trans, on Nuclear Science, Vol. 35, No. 1, Feb. 1988.
2. "ALICE technical proposal", CERN/LHCC 95-71, Dec. 95.
3. T. E. Rahkonen et al., "The use of stabilized CMOS delay lines for the digitization of short time intervals", IEEE J. of Solid-State Circuits, Vol. 28, No. 8, pp. 887-894, Aug. 1993.
4. Y. Arai et al., "A time digitizer CMOS gate-array with 250 ps time resolution", IEEE J. of Solid-State Circuits, Vol. 31, No. 2, pp. 212-220, Feb. 1996.
5. J. Christiansen, "An integrated high resolution CMOS timing generator based on an array of delay locked loops", IEEE J. of Solid-State Circuits, Vol. 31, No. 7, pp. 952-957, July 1996.
6. M. Pelgrom et all, "Matching Proprieties of MOS Transistors", IEEE J. of Solid-State Circuits, Vol. 24, No. 5, pp. 1433-1429, Oct. 1989.
7. M. Johnson et all, "A variable delay line for CPU co-processor synchronization", IEEE J. of Solid-State Circuits, Vol. 23, No. 23, pp. 1218-1223, Oct. 1988.