Digitally-controlled DLL and I/O circuits for 500Mb/s/pin ×16 DDR SDRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 68-69+431

  Lee, J B ^a   Kim, K H ^a   Yoo, C ^a   Lee, S ^a   Na, O G ^a   Lee, C Y ^a   Song, H Y ^a   Lee, J S ^a   Lee, Z H ^a   Yeom, K W ^a   Chung, H J ^a   Seo, I W ^a   Chae, M S ^a   Choi, Y H ^a   Cho, S I ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; FLIP FLOP CIRCUITS; JITTER; MICROPROCESSOR CHIPS;

DELAY LOCKED LOOPS (DLL);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035063430     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A portable digital DLL for high-speed CMOS interface circuits
2. A CMOS 50% duty cycle repeater using complementary phase blending
3. A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs