An ultra-low-power fast-lock-in small-jitter all-digital DLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Wang, Jinn Shyan ^a   Wang, Yi Ming ^a   Chen, Chin Hao ^a   Liu, Yu Chia ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144463230     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. G.K. Dehng et al., "Clock-deskew Buffer Using a SAR-Controlled Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 35, pp. 1128-1135, Aug., 2000.
2. J. J. Kim et al., "A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications," IEEE J. Solid-State Circuits, vol. 35, pp.1430-1436, Oct., 2000.
3. G.K. Dehng et al., "A Fast-Lock Mixed-Mode DLL Using a 2b SAR Algorithm," IEEE J. Solid-State Circuits, vol. 36, pp. 1464-1471, Oct., 2001.
4. B.S. Kong et al., "Conditional-Capture Flip-Flop for Statistical Power Reduction," IEEE J. Solid-State Circuits, vol. 36, pp. 1263-1271, Aug., 2001.