Clock duty cycle adjuster circuit for switched capacitor circuits

Electronics Letters

Volumn 38, Issue 18, 2002, Pages 1008-1009

  Karthikeyan, S ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC CURRENTS; ELECTRIC DELAY LINES; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; OPERATIONAL AMPLIFIERS; PHASE LOCKED LOOPS; SWITCHING CIRCUITS;

CLOCK DUTY CYCLE ADJUSTER CIRCUIT; FREQUENCY TO VOLTAGE CONVERTER; PIPELINED DATA CONVERTERS; PULSE WIDTH LOCKED LOOP; PULSED WIDTH DETECTOR; SWITCHED CAPACITOR CIRCUITS; VOLTAGE CONTROLLED DELAY LINES;

TIMING CIRCUITS;

EID: 0037194838     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020657     Document Type: Article

References (5)

1. Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
2. A CMOS 50% duty cycle repeater using complementary phase blending
3. A 700 Mbps/pin CMOS signaling interface using current integrating receivers
4. High performance integrated CMOS frequency to voltage converter
5. Precise delay generation using coupled oscillations