Optimality study of logic synthesis for LUT-based FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2006, Pages 33-40

  Cong, Jason ^a   Minkovich, Kirill ^a  

^a Engineering IV   (United States)

Author keywords

Boolean Logic; FPGA Lookup Table; Logic Synthesis; Optimization; Technology Mapping

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; INFORMATION TECHNOLOGY; MAPPING; OPTIMIZATION; PROBLEM SOLVING; TABLE LOOKUP;

BOOLEAN LOGIC; FPGA LOOKUP TABLE; LOGIC SYNTHESIS; TECHNOLOGY MAPPING;

LOGIC DESIGN;

EID: 33745824652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1117201.1117207     Document Type: Conference Paper

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