Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 730-733

  Legl, Christian ^a   Wurth, Bernd ^a   Eckl, Klaus ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC VARIABLES CONTROL; EQUIVALENCE CLASSES; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC DESIGN;

FIELD PROGRAMMABLE GATE ARRAYS (FPGAS); FUNCTIONAL DECOMPOSITION ALGORITHM; ROUTING;

LOGIC GATES;

EID: 0029708450     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)