Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 748-751

  Teslenko, Maxim ^a   Dubrova, Elena ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL METHODS; GRAPH THEORY; HEURISTIC METHODS; PARAMETER ESTIMATION; SET THEORY; TABLE LOOKUP;

BOOLEAN CIRCUITS; DELAY OPTIMIZATION; DEPTH MINIMIZATION; PRIMARY INPUTS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 16244401635     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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