-
1
-
-
0035465564
-
TCAD development for lithography resolution enhancement
-
L. W. Liebmann, S. M. Mansfield, A. K. Wong, M. A. Lavin, W. C. Leipold, and T. G. Dunham. "TCAD development for lithography resolution enhancement." IBM Journal of Research and Development, vol.45, no. 5, 2001.
-
(2001)
IBM Journal of Research and Development
, vol.45
, Issue.5
-
-
Liebmann, L.W.1
Mansfield, S.M.2
Wong, A.K.3
Lavin, M.A.4
Leipold, W.C.5
Dunham, T.G.6
-
2
-
-
24644435944
-
Spanos C'comprehensive CD uniformity control across lithography and etch
-
Qiaolin Zhang, Tang C, Hsieh T,Maccrae N, Singh B, Poolla K, Spanos C'Comprehensive CD Uniformity Control across Lithography and Etch." SPIE, vol. 5755, 2005.
-
(2005)
SPIE
, vol.5755
-
-
Zhang, Q.1
Tang, C.2
Hsieh, T.3
Maccrae, N.4
Singh, B.5
Poolla, K.6
-
3
-
-
4344694577
-
Across-wafer CD uniformity enhancement through control of multi-zone PEB profiles
-
24 May. USA
-
Qiaolin Zhang, Friedberg PD, Cherry Tang, Singh B, Poolla K, Spanos CJ. "Across-wafer CD uniformity enhancement through control of multi-zone PEB profiles. SPIE, vol.5375, no.1, 24 May 2004, pp.276-86. USA.
-
(2004)
SPIE
, vol.5375
, Issue.1
, pp. 276-286
-
-
Zhang, Q.1
Friedberg, P.D.2
Tang, C.3
Singh, B.4
Poolla, K.5
Spanos, C.J.6
-
4
-
-
0036575868
-
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
-
May USA
-
Orshansky M, Milor L, Pinhong Chen, Keutzer K, Chenming Hu. "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol.21, no.5, May 2002, pp.544-53, USA.
-
(2002)
IEEE Transactions on Computer-aided Design of Integrated Circuits & Systems
, vol.21
, Issue.5
, pp. 544-553
-
-
Orshansky, M.1
Milor, L.2
Chen, P.3
Keutzer, K.4
Hu, C.5
-
6
-
-
0037999075
-
Layout optimization at the pinnacle of optical lithography
-
USA
-
Liebmann LW, Northrop GA, Gulp J, Sigal L, Barish A, Fonseca CA. "Layout optimization at the pinnacle of optical lithography." SPIE, vol.5042, 2003, pp. 1-14. USA.
-
(2003)
SPIE
, vol.5042
, pp. 1-14
-
-
Liebmann, L.W.1
Northrop, G.A.2
Gulp, J.3
Sigal, L.4
Barish, A.5
Fonseca, C.A.6
-
7
-
-
0042635594
-
Exploring regular fabrics to optimize the performance-cost trade-off
-
IEEE. Piscataway, NJ, USA
-
Pileggi L, Schmit H, Strojwas AJ, Gopalakrishnan P, Kheterpal V, Koorapaty A, Patel C, Rovner V, Tong KY. "Exploring regular fabrics to optimize the performance-cost trade-off." Design Automation Conference, IEEE. 2003, pp. 782-7. Piscataway, NJ, USA.
-
(2003)
Design Automation Conference
, pp. 782-787
-
-
Pileggi, L.1
Schmit, H.2
Strojwas, A.J.3
Gopalakrishnan, P.4
Kheterpal, V.5
Koorapaty, A.6
Patel, C.7
Rovner, V.8
Tong, K.Y.9
-
8
-
-
27944478180
-
-
IEEE. Los Alamitos, CA, USA
-
Raghvendra S, Hurat P. "DFM: linking design and manufacturing." IEEE, 2005, pp. 705-8. Los Alamitos, CA, USA.
-
(2005)
DFM: Linking Design and Manufacturing
, pp. 705-708
-
-
Raghvendra, S.1
Hurat, P.2
-
9
-
-
0346778720
-
Manufacturing-aware physical design
-
Piscataway, NJ, USA
-
Gupta P, Kahng AB. "Manufacturing-aware physical design." ICCAD-2003 IEEE. 2003, pp.681-7. Piscataway, NJ, USA.
-
(2003)
ICCAD-2003 IEEE
, pp. 681-687
-
-
Gupta, P.1
Kahng, A.B.2
-
10
-
-
3042624707
-
Logic synthesis for manufacturability
-
May-June. USA
-
Nardi A, Sangiovanni-Vincentelli AL. "Logic synthesis for manufacturability." IEEE Design & Test of Computers, vol.21, no.3, May-June 2004, pp. 192-9. USA.
-
(2004)
IEEE Design & Test of Computers
, vol.21
, Issue.3
, pp. 192-199
-
-
Nardi, A.1
Sangiovanni-Vincentelli, A.L.2
-
12
-
-
24644494019
-
Advanced timing analysis based on post-OPC patterning process simulations
-
USA
-
Jie Yang, Capodieci L, Sylvester D. "Advanced timing analysis based on post-OPC patterning process simulations." SPIE, vol.5756, no.1, 2005, pp. 189-97. USA.
-
(2005)
SPIE
, vol.5756
, Issue.1
, pp. 189-197
-
-
Yang, J.1
Capodieci, L.2
Sylvester, D.3
-
14
-
-
2942670511
-
Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology
-
USA
-
Dusa M, Moerman R, Singh B, Friedberg P, Hoobler R, Zavecz T. "Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology." SPIE, vol.5378, no.1, 2004, pp.93-104. USA.
-
(2004)
SPIE
, vol.5378
, Issue.1
, pp. 93-104
-
-
Dusa, M.1
Moerman, R.2
Singh, B.3
Friedberg, P.4
Hoobler, R.5
Zavecz, T.6
-
15
-
-
84886673851
-
Modeling within-die spatial correlation effects for process-design co-optimization
-
Los Alamitos, CA, USA
-
Friedberg P, Cao Y, Cain J, Wang R, Rabaey J, Spanos C. "Modeling within-die spatial correlation effects for process-design co-optimization." IEEE Comput. Soc. 2005, pp.516-21. Los Alamitos, CA, USA.
-
IEEE Comput. Soc. 2005
, pp. 516-521
-
-
Friedberg, P.1
Cao, Y.2
Cain, J.3
Wang, R.4
Rabaey, J.5
Spanos, C.6
-
16
-
-
2942648510
-
A methodology to analyze circuit impact of process-related MOSFET geometry
-
USA
-
Balasinski A. "A methodology to analyze circuit impact of process-related MOSFET geometry." SPIE, vol.5379, no.1, 2004, pp. 85-92. USA
-
(2004)
SPIE
, vol.5379
, Issue.1
, pp. 85-92
-
-
Balasinski, A.1
-
17
-
-
33745801065
-
65-nm gate OPC optimization with simple electrical model simulation
-
Y. Trouiller, et al "65-nm gate OPC optimization with simple electrical model simulation" SPIE, vol.5756, no.38, 2005
-
(2005)
SPIE
, vol.5756
, Issue.38
-
-
Trouiller, Y.1
-
18
-
-
33745608353
-
From poly line to transistor: Building BSIM models for non-rectangular transistors
-
Poppe W, Capodieci L, and Neureuther A. "From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors." SPIE, vol. 6156, no.26, 2006.
-
(2006)
SPIE
, vol.6156
, Issue.26
-
-
Poppe, W.1
Capodieci, L.2
Neureuther, A.3
-
19
-
-
0036049629
-
A general probabilistic framework for worst case timing analysis
-
New York, NY, USA
-
Orshansky M, Keutzer K. "A general probabilistic framework for worst case timing analysis." Proceedings 2002 Design Automation Conference. 2002, pp.556-61. New York, NY, USA.
-
(2002)
Proceedings 2002 Design Automation Conference
, pp. 556-561
-
-
Orshansky, M.1
Keutzer, K.2
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