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Volumn 6156, Issue , 2006, Pages

Platform for collaborative DFM

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGN; ENHANCED TRANSISTORS; PARAMETRIC YIELD SIMULATORS; PROCESS FLOW;

EID: 33745805182     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.657042     Document Type: Conference Paper
Times cited : (10)

References (19)
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    • Qiaolin Zhang, Tang C, Hsieh T,Maccrae N, Singh B, Poolla K, Spanos C'Comprehensive CD Uniformity Control across Lithography and Etch." SPIE, vol. 5755, 2005.
    • (2005) SPIE , vol.5755
    • Zhang, Q.1    Tang, C.2    Hsieh, T.3    Maccrae, N.4    Singh, B.5    Poolla, K.6
  • 3
    • 4344694577 scopus 로고    scopus 로고
    • Across-wafer CD uniformity enhancement through control of multi-zone PEB profiles
    • 24 May. USA
    • Qiaolin Zhang, Friedberg PD, Cherry Tang, Singh B, Poolla K, Spanos CJ. "Across-wafer CD uniformity enhancement through control of multi-zone PEB profiles. SPIE, vol.5375, no.1, 24 May 2004, pp.276-86. USA.
    • (2004) SPIE , vol.5375 , Issue.1 , pp. 276-286
    • Zhang, Q.1    Friedberg, P.D.2    Tang, C.3    Singh, B.4    Poolla, K.5    Spanos, C.J.6
  • 9
    • 0346778720 scopus 로고    scopus 로고
    • Manufacturing-aware physical design
    • Piscataway, NJ, USA
    • Gupta P, Kahng AB. "Manufacturing-aware physical design." ICCAD-2003 IEEE. 2003, pp.681-7. Piscataway, NJ, USA.
    • (2003) ICCAD-2003 IEEE , pp. 681-687
    • Gupta, P.1    Kahng, A.B.2
  • 12
    • 24644494019 scopus 로고    scopus 로고
    • Advanced timing analysis based on post-OPC patterning process simulations
    • USA
    • Jie Yang, Capodieci L, Sylvester D. "Advanced timing analysis based on post-OPC patterning process simulations." SPIE, vol.5756, no.1, 2005, pp. 189-97. USA.
    • (2005) SPIE , vol.5756 , Issue.1 , pp. 189-197
    • Yang, J.1    Capodieci, L.2    Sylvester, D.3
  • 14
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    • Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology
    • USA
    • Dusa M, Moerman R, Singh B, Friedberg P, Hoobler R, Zavecz T. "Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology." SPIE, vol.5378, no.1, 2004, pp.93-104. USA.
    • (2004) SPIE , vol.5378 , Issue.1 , pp. 93-104
    • Dusa, M.1    Moerman, R.2    Singh, B.3    Friedberg, P.4    Hoobler, R.5    Zavecz, T.6
  • 15
    • 84886673851 scopus 로고    scopus 로고
    • Modeling within-die spatial correlation effects for process-design co-optimization
    • Los Alamitos, CA, USA
    • Friedberg P, Cao Y, Cain J, Wang R, Rabaey J, Spanos C. "Modeling within-die spatial correlation effects for process-design co-optimization." IEEE Comput. Soc. 2005, pp.516-21. Los Alamitos, CA, USA.
    • IEEE Comput. Soc. 2005 , pp. 516-521
    • Friedberg, P.1    Cao, Y.2    Cain, J.3    Wang, R.4    Rabaey, J.5    Spanos, C.6
  • 16
    • 2942648510 scopus 로고    scopus 로고
    • A methodology to analyze circuit impact of process-related MOSFET geometry
    • USA
    • Balasinski A. "A methodology to analyze circuit impact of process-related MOSFET geometry." SPIE, vol.5379, no.1, 2004, pp. 85-92. USA
    • (2004) SPIE , vol.5379 , Issue.1 , pp. 85-92
    • Balasinski, A.1
  • 17
    • 33745801065 scopus 로고    scopus 로고
    • 65-nm gate OPC optimization with simple electrical model simulation
    • Y. Trouiller, et al "65-nm gate OPC optimization with simple electrical model simulation" SPIE, vol.5756, no.38, 2005
    • (2005) SPIE , vol.5756 , Issue.38
    • Trouiller, Y.1
  • 18
    • 33745608353 scopus 로고    scopus 로고
    • From poly line to transistor: Building BSIM models for non-rectangular transistors
    • Poppe W, Capodieci L, and Neureuther A. "From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors." SPIE, vol. 6156, no.26, 2006.
    • (2006) SPIE , vol.6156 , Issue.26
    • Poppe, W.1    Capodieci, L.2    Neureuther, A.3
  • 19
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    • A general probabilistic framework for worst case timing analysis
    • New York, NY, USA
    • Orshansky M, Keutzer K. "A general probabilistic framework for worst case timing analysis." Proceedings 2002 Design Automation Conference. 2002, pp.556-61. New York, NY, USA.
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    • Orshansky, M.1    Keutzer, K.2


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