메뉴 건너뛰기




Volumn , Issue , 2005, Pages 117-129

Run-time defragmentation for dynamically reconfigurable hardware

Author keywords

active function; defragmentation; dynamic relocation; fragmentation; partial and dynamic reconfiguration; Reconfigurable computing

Indexed keywords


EID: 33745756000     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-3128-9_10     Document Type: Chapter
Times cited : (9)

References (20)
  • 1
    • 0035242921 scopus 로고    scopus 로고
    • A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs
    • Feb. 2001
    • Cantó, E., J. M. Moreno, J. Cabestany, I. Lacadena, and J. M. Insenser. (2001). "A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs", IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 210-218.
    • (2001) IEEE Trans. on VLSI Systems , vol.9 , Issue.1 , pp. 210-218
    • Cantó, E.1    Moreno, J.M.2    Cabestany, J.3    Lacadena, I.4    Insenser, J.M.5
  • 2
    • 0142035525 scopus 로고    scopus 로고
    • An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
    • Cardoso, J. M. P., and H. C. Neto. (1999). "An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs", Proc. 10th Intl. Conf. on VLSI, pp. 485-496.
    • (1999) Proc. 10th Intl. Conf. on VLSI , pp. 485-496
    • Cardoso, J.M.P.1    Neto, H.C.2
  • 3
    • 0036625327 scopus 로고    scopus 로고
    • Configuration, relocationand defragmentation for run-time reconfigurable computing
    • June 2002
    • Compton, K., Z. Li, J. Cooley, S. Knol, and S. Hauck. (2002). "Configuration, Relocationand Defragmentation for Run-Time Reconfigurable Computing", IEEE Trans. on VLSI Systems, Vol. 10, No. 3, June 2002, pp. 209-220.
    • (2002) IEEE Trans. on VLSI Systems , vol.10 , Issue.3 , pp. 209-220
    • Compton, K.1    Li, Z.2    Cooley, J.3    Knol, S.4    Hauck, S.5
  • 8
  • 10
    • 0002165396 scopus 로고    scopus 로고
    • Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
    • Kaul, M., and R. Vemuri. (1999). "Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs", Proc. Design, Automation and Test in Europe, pp. 202-209.
    • (1999) Proc. Design, Automation and Test in Europe , pp. 202-209
    • Kaul, M.1    Vemuri, R.2
  • 11
    • 0036382691 scopus 로고    scopus 로고
    • Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation
    • Field-Programmable Gate Arrays
    • Li, Z., and S. Hauck. (2002). "Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation" , Proc. 10th ACM Int. Symp. Field-Programmable Gate Arrays, pp. 187-195.
    • (2002) Proc. 10th ACM Int. Symp , pp. 187-195
    • Li, Z.1    Hauck, S.2
  • 13
    • 0035242943 scopus 로고    scopus 로고
    • A formal approach to context scheduling for multicontext reconfigurable architectures
    • Feb. 2001
    • Maestre, R., F. J. Kurdahi, R. Hermida, N. Bagherzadeh, and H. Singh. (2001). "A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures", IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173-185.
    • (2001) IEEE Trans. on VLSI Systems , vol.9 , Issue.1 , pp. 173-185
    • Maestre, R.1    Kurdahi, F.J.2    Hermida, R.3    Bagherzadeh, N.4    Singh, H.5
  • 16
    • 0034187952 scopus 로고    scopus 로고
    • MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
    • May 2000
    • Singh, H., M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. (2000). "MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications", IEEE Trans. on Computers, Vol. 49, No. 5, May 2000, pp. 465-481.
    • (2000) IEEE Trans. on Computers , vol.49 , Issue.5 , pp. 465-481
    • Singh, H.1    Lee, M.-H.2    Lu, G.3    Kurdahi, F.J.4    Bagherzadeh, N.5    Filho, E.M.C.6
  • 18
    • 0031618686 scopus 로고    scopus 로고
    • Scheduling designs into a time-multiplexed FPGA
    • Field Programmable Gate Arrays
    • Trimberger, S. (1998). "Scheduling designs into a time-multiplexed FPGA", Proc. Int. Symp. Field Programmable Gate Arrays, pp. 153-160.
    • (1998) Proc. Int. Symp , pp. 153-160
    • Trimberger, S.1
  • 19
    • 0012733099 scopus 로고    scopus 로고
    • DYNASTY: A temporal floorplanning based CAD framework for dynamically reconfigurable logic systems
    • Vasilko, M. (1999). "DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems", Proc. 9th Intl. Workshop on Field-Programmable Logic and Applications, pp. 124-133.
    • (1999) Proc. 9th Intl. Workshop on Field-programmable Logic and Applications , pp. 124-133
    • Vasilko, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.