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Volumn , Issue , 2003, Pages 974-979

Run-time management of logic resources on reconfigurable systems

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMICALLY RECONFIGURABLE SYSTEMS; EFFICIENT MANAGEMENTS; LOGIC RESOURCES; RECONFIGURABLE; RECONFIGURABLE SYSTEMS; RESOURCE ALLOCATION DECISION; RUNTIME MANAGEMENT; TOOL USE;

EID: 84893746344     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253731     Document Type: Conference Paper
Times cited : (33)

References (13)
  • 2
    • 0142035525 scopus 로고    scopus 로고
    • An enhanced static-list scheduling algorithm for temporal partitioning onto rpus
    • J.M.P Cros, H.C. Neto, An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs, Proc. 10th Intl. Conf. on VLSI, 1999, pp. 485-496
    • (1999) Proc. 10th Intl. Conf. on VLSI , pp. 485-496
    • Cardoso, J.M.P.1    Neto, H.C.2
  • 3
    • 0035242943 scopus 로고    scopus 로고
    • A formal approach to context scheduling for multicontext reconfigurable architectures
    • Feb
    • R. Maestre, F.J. Kurdahi, R. Hermida, N. Bagherzadeh, H. Singh, A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures, IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173-185
    • (2001) IEEE Trans. on VLSI Systems , vol.9 , Issue.1 , pp. 173-185
    • Maestre, R.1    Kurdahi, F.J.2    Hermida, R.3    Bagherzadeh, N.4    Singh, H.5
  • 6
    • 0012733099 scopus 로고    scopus 로고
    • Dynasty: A temporal floorplanning based cad framework for dynamically reconfigurable logic systems
    • M. Vasilko, DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems, Proc. 9th Intl. Workshop on Field-Programmable Logic and Applications, 1999, pp.124-133
    • (1999) Proc. 9th Intl. Workshop on Field-Programmable Logic and Applications , pp. 124-133
    • Vasilko, M.1
  • 11
    • 84893730282 scopus 로고
    • IEEE Std. Test Access Port and Boundary Scan Architecture May
    • IEEE Std. Test Access Port and Boundary Scan Architecture (IEEE Std 1149.1), IEEE Std. Board, May 1990
    • (1990) IEEE Std 1149.1 IEEE Std. Board


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.