A formal approach to context scheduling for multicontext reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 173-185

  Maestre, Rafael ^b   Kurdahi, Fadi J ^c   Fernández, Milagros ^b   Hermida, Roman ^b   Bagherzadeh, Nader ^a,c   Singh, Hartej ^a,c  

^a IEEE

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Performance tradeoffs; Reconfigurable computing; System level

Indexed keywords

ALGORITHMS; FORMAL LOGIC; HEURISTIC METHODS; OPTIMIZATION; TIME DOMAIN ANALYSIS;

CONTEXT SCHEDULING; MULTICONTEXT RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE SYSTEMS;

VLSI CIRCUITS;

EID: 0035242943     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920831     Document Type: Article

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