DYNASTY: A temporal floorplanning based cad framework for dynamically reconfigurable logic systems

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1673, Issue , 1999, Pages 124-133

  Vasilko, Milan ^a  

^a BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

DESIGN ABSTRACTIONS; DESIGN ITERATION; DESIGN METHODOLOGY; DESIGN SPACE EXPLORATION; DESIGN TECHNIQUE; DYNAMICALLY RECONFIGURABLE LOGIC; TEMPORAL DIMENSIONS; TEMPORAL FLOORPLANNING;

RECONFIGURABLE HARDWARE;

EID: 0012733099     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-48302-1_13     Document Type: Conference Paper

References (14)

1. M. Vasilko, D. Gibson, D. Long, and S. Holloway, "Towards a consistent design methodology for run-time reconfigurable systems," in IEE Colloquium on Reconfigurable Systems, Digest No.99/061, Glasgow, Scotland, pp. 5/1-4, Mar. 10 1999.
2. P. Lysaght, "Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic," in Luk et al. [14], pp. 183-192.
3. M. Kaul and R. Vemuri, "Optimal temporal partitioning and synthesis for reconfigurable architectures," in Design, Automation and Test in Europe Conference, Paris, France, Feb. 23-26, 1998.
4. M. Vasilko and D. Ait-Boudaoud, "Architectural synthesis techniques for dynamically reconfigurable logic," in Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, (Proc. FPL'96) (R. W. Hartenstein and M. Glesner, eds.), LNCS 1142, pp. 290-296, Springer-Verlag, 1996.
5. K. Bazargan, R. Kaster, and M. Sarrafzadeh, "3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems," in Proc. IEEE Workshop on Rapid System Prototyping (RSP'99), Clearwater, FL, USA, June 16-18, 1999.
6. Xilinx, XC6200 Field Programmable Gate Arrays, Advanced Product Information Xilinx, Inc., Apr. 1997. Version 1.10.
7. P. Lysaght and J. Stockwood, "A simulation tool for dynamically reconfigurable field programmable gate arrays," IEEE Transactions on VLSI Systems, vol. 4, no. 3, pp. 381-390, Sept. 1996.
8. M. Vasilko and D. Cabanis, "Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems," in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99), Napa, CA, USA, Apr. 21-23, 1999.
9. P. Stanford and P. Mancuso, eds., EDIF Electronic Design Interchange Format Version 2 0 0. Electronic Industries Association, 2nd ed., 1990.
10. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Luk et al. [14], pp. 213-222.
11. P. Foulk and I. Hodson, "Data folding in SRAM configurable FPGAs," in Proc. IEEE Workshop on FPGAs for Custom Computing Machines (D. A. Buell and K. L. Pocek, eds.), Napa, CA, USA, Apr. 5-7, 1993.
12. P. Dewilde, E. Deprettere, and R. Nouta, "Parallel and pipelined VLSI implementation of signal processing algorithms," in VLSI and Modern Signal Processing (S. Kung, H. Whitehouse, and T. Kailath, eds.), pp. 257-264, Prentice Hall, 1985.
13. P. G. Paulin and J. P. Knight, "Algorithms for high-level synthesis," IEEE Design and Test of Computers, vol. 6, no. 3, pp. 18-31, Dec. 1989.
14. W. Luk, P. Y. K. Cheung, and M. Glesner, eds., Field Programmable Logic and Applications (Proc. FPL'97), LNCS 1304, Springer-Verlag, 1997.