A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 210-218

  Canto E ^a   Moreno, J M ^a   Cabestany, Joan ^a   Lacadena, I ^b   Insenser, J M ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b PTM   (Spain)

Author keywords

DRFPGA; Dynamically reconfigurable FPGA; FIPSOC; Temporal bipartitioning

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; DIGITAL INTEGRATED CIRCUITS; LOGIC DESIGN; REAL TIME SYSTEMS;

DYNAMICALLY RECONFIGURABLE FIELD PROGRAMMABLE GATE ARRAYS; SYNCHRONOUS DIGITAL SYSTEMS; TEMPORAL BIPARTITIONING ALGORITHM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035242921     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920836     Document Type: Article

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