On-line defragmentation for run-time partially reconfigurable FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 302-311

  Gericota, Manuel G ^a   Alves, Gustavo R ^a   Silva, Miguel L ^b   Ferreira, José M ^b  

^a INSTITUTO SUPERIOR DE ENGENHARIA DO PORTO   (Portugal)

^b UNIVERSITY OF PORTO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES;

ACTIVE REPLICATION; CONFIGURABLE LOGIC BLOCKS; DE-FRAGMENTATION; DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE SYSTEMS; INDEPENDENT FUNCTIONS; RECONFIGURABLE; RESOURCE ALLOCATION DECISION;

RECONFIGURABLE HARDWARE;

EID: 34548360973     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_32     Document Type: Conference Paper

References (10)

1. th Intl. Conf. on Very Large Scale Integration, Lisbon, Portugal, 1999, pp. 485-496.
2. Maestre, R., Kurdahi, F. J., Hermida, R., Bagherzadeh, N., Singh, H., A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures. IEEE Transactions on Very Large Scale Integration Systems, Vol. 9, No. 1, February 2001, pp. 173-185. (Pubitemid 32922822)
3. Sanchez-Elez, M., Fernandez, M., Maestre, R., Hermida, R., Bagherzadeh, N., Kurdahi, F. J.: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. Proc. of the Design, Automation and Test in Europe, Paris, France, 2002, pp. 547-552.
4. Diessel, O., ElGindy, H., Middendorf, M., Schmeck, H., Schmidt, B.: Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proc.-Computer Digital Technology, Vol. 147, No. 3, May 2000, pp. 181-188.
5. th International Workshop on Field-Programmable Logic and Applications, Glasgow, Scotland, 1999, pp.124-133.
6. Teich, M., Fekete, S., Schepers, J.: Compile-time optimization of dynamic hardware reconfigurations. Proc. of the Intl. Conf. on Parallel and Distributed Processing Techniques and Applications, Las Vegas, USA, 1999.
7. nd IEEE Latin-American Test Workshop Digest of Papers, Montevideo, Uruguay, 2002, pp. 70-75.
8. Politøcnico di Torino ITC 99 benchmarks. http://www.cad.polito.it/ tools/itc99.html
9. IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std 1149.1), IEEE Std. Board, May 1990.
10. th ACM Int. Symposium on Field-Programmable Gate Arrays, Monterey, California, 2001, pp. 183-192. (Pubitemid 32456849)