Modeling dual inlaid feature construction

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 24, Issue 3, 2006, Pages 1344-1352

  Stout, Phillip J ^a   Rauf, Shahid ^a   Nagy, Andrew ^a   Ventzek, Peter L G ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC ETCH RATIO; DUAL INLAID (DI); FLUOROCARBON PLASMA ETCHING; VIA FIRST TRENCH LAST (VFTL) DI;

ETCHING; FEATURE EXTRACTION; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; METALLIZING; PLASMA APPLICATIONS;

COPPER;

EID: 33744788373     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.2198850     Document Type: Article

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