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1
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-
0242453571
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-
note
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2)-active wiring only, excluding global levels") on page 75. On 5/2003 a pdf copy of this document was found available for download at
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2
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0242621965
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Impact of interconnect architecture on chip size and die yield
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(IEEE Electron Devices Society, New York)
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R. Liu, C. Pai, H. Cong, W. Lai and E. Martinez Impact of Interconnect Architecture on Chip Size and Die Yield, Proceedings of the International Interconnect Technology Conference (IITC) (IEEE Electron Devices Society, New York) 1999, pp. 21-23.
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Proceedings of the International Interconnect Technology Conference (IITC)
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Liu, R.1
Pai, C.2
Cong, H.3
Lai, W.4
Martinez, E.5
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3
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0029547914
-
Interconnect scaling - The real limiter to high performance ULSI
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(IEEE International Electron Devices Society)
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M.T. Bohr Interconnect Scaling - The Real Limiter to High Performance ULSI (IEEE International Electron Devices Society) 1995, pp. 241-244.
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6
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A. Deutsch, P.W. Coteus, G.V. Kopcsay, H.H. Smith, C.W. Surovic, B.L. Krauter, L. Krauter, D.C. Edelstein and P.J. Restel Proc. IEEE 89, 529 (2001).
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Deutsch, A.1
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Krauter, L.7
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11
-
-
0003608733
-
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note; (W.H. Freeman Co.)
-
Local interconnects are expected to have cross-sectional dimensions in the deep submicron regime. At 5 GHz, most candidate conducting materials exhibit rf skin depths in a range extending from 0.9 to 1.3 μm. P. Lorrain and D. Corson Electromagnetic Fields and Waves, 2nd ed. (W.H. Freeman Co.) pp. 478-479.
-
Electromagnetic Fields and Waves, 2nd Ed.
, pp. 478-479
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Lorrain, P.1
Corson, D.2
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17
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0242621961
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(private communication, IBM Corporation)
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D.C. Edelstein (private communication, IBM Corporation).
-
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Edelstein, D.C.1
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18
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0242621488
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"The integration of copper metallization and low k dielectrics for ULSI and interconnects, and its reliability," an electrochemical society short course
-
see p. 16 of course notes for properties of candidate metals
-
H. Rathore and D.B. Nguyen "The Integration of Copper Metallization and Low k Dielectrics for ULSI and Interconnects, and Its Reliability," an Electrochemical Society Short Course, 1999, see p. 16 of course notes for properties of candidate metals.
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(1999)
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Rathore, H.1
Nguyen, D.B.2
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0346274468
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edited by R. Cheung, J. Klein, K. Tsubouchi, M. Murakami, and N. Kobayashi (Materials Research Society, Pittsburgh, PA)
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R. Venkatraman et al., in Advanced Metallization and Interconnect Systems for ULSI Applications in 1997, edited by R. Cheung, J. Klein, K. Tsubouchi, M. Murakami, and N. Kobayashi (Materials Research Society, Pittsburgh, PA, 1997), p. 63.
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Advanced Metallization and Interconnect Systems for ULSI Applications in 1997
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Venkatraman, R.1
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0242453042
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note
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Encyclopedia Britannica, as accessed online on 5/1/2003 at (keyword: damascening).
-
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31
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0242536731
-
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Hammering is not one of them
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Hammering is not one of them.
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32
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0242536732
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U.S. Patent 4,702,792 (27 October)
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M. Chow, W. L. Guthrie, and F. B. Kaufman, U.S. Patent 4,702,792 (27 October, 1987).
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C. W. Kaanta et al., Proceedings of the 8th International IEEE VLSI Multilevel Interconnect Conference, Santa Clara, CA, 1991, pp. 144-152.
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Proceedings of the 8th International IEEE VLSI Multilevel Interconnect Conference, Santa Clara, CA, 1991
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(IEEE Electron Devices Society, New York)
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C. Verove, B. Descouts, P. Gayet, M. Gillermet, E. Sabouret, P. Spinelli, and E. Van der Vegt, Proceedings of the International Interconnect Technology Conference (IITC) (IEEE Electron Devices Society, New York, 2000), pp. 267-269.
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Verove, C.1
Descouts, B.2
Gayet, P.3
Gillermet, M.4
Sabouret, E.5
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Van Der Vegt, E.7
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40
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0242705656
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(Private communication, Novellus Corporation)
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Gary Ray (Private communication, Novellus Corporation).
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(private communication, IBM Corporation)
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S. M. Rossnagel (private communication, IBM Corporation).
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Rossnagel, S.M.1
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44
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0242621495
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(private communication, Clariant, AZ)
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R. Dammel (private communication, Clariant, AZ).
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Dammel, R.1
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47
-
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85088341279
-
-
note
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DB) for standard oxides is about 10 MV/cm and in the range of about 6 MV/cm for most low-k materials presently being considered.
-
-
-
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48
-
-
0242705663
-
-
note
-
Supported by the International Technology Roadmap (ITRS) 2001, numerous papers presented at the International Interconnect Technology Conference (IITC) 2002 and the authors' direct experience with semiconductor manufacturers.
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49
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0242706710
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D. Keil, D. Cooperberg, L. Li, G. Mueller, T. Nguyen, K. Khajehnouri, V. Vahedi, and G. Hills, Proc.-Electrochem. Soc. 98, 114 (1998).
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Vahedi, V.7
Hills, G.8
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52
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0003608733
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note
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P. Lorrain and D. L. Corson, Electromagnetic Fields and Waves, 2nd ed. (W.H. Freeman Co). Estimates of this type assume an infinite parallel plate capacitor, then use standard "Gaussian pillbox" arguments. An example can be found on page 110 of this text. Note that only a capacitance ratio is relevant here. Effects due to fringe fields that do not intersect the stop layer tend to cancel our for such ratios.
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Electromagnetic Fields and Waves, 2nd Ed.
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Lorrain, P.1
Corson, D.L.2
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54
-
-
0242536738
-
-
note
-
The thickness range given is based on the direct experience of the authors with semiconductor manufacturers. However, one can also roughly estimate this range using the ITRS roadmap. Table 46a of the Interconnect section of the ITRS 2000 roadmap gives "pitch" and "via A/R" (aspect ratio) values for 1999 to the present. One can now assume these values are used in volume manufacturing. ILD thickness is then estimated as the pitch times the via A/R ESL is then roughly estimated as 5% of the ILD thickness. On 5/16/2003, a PDF copy of the interconnect section of the ITRS 2000 roadmap was found available for download at
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D. Keil, E. Wagganer, and B. A. Helmer, U.S.Patent No. 6,540,885 B1 (April 2003).
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Proceedings of the 45th International Symposium of the American Vacuum Society, Baltimore, MD, November 2-6, 1998
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Vahedi, V.1
Cooperberg, D.J.2
Cook, J.M.3
Marquez, L.4
Hudson, E.A.5
Winniczek, J.6
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V. Vahedi, J. Daugherty, S. Huang, D. Cooperberg, R. A. Gottscho, H. J. Tao, H. J. Lin, C. S. Tsai, and M. S. Liang, Proceedings of the 21st Symposium on Dry Process, Dry Process Symposium, Tokyo, November 11-12, 1999, pp. 111-113.
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Proceedings of the 21st Symposium on Dry Process, Dry Process Symposium, Tokyo, November 11-12, 1999
, pp. 111-113
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Vahedi, V.1
Daugherty, J.2
Huang, S.3
Cooperberg, D.4
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Tao, H.J.6
Lin, H.J.7
Tsai, C.S.8
Liang, M.S.9
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V. Vahedi, S. Lin, H. W. Chang, H. J. Tao, C. C. Chen, C S. Tsai, and M. S. Liang, 46th International Symposium of the American Vacuum Society, Seattle, October 25-29, 1999.
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46th International Symposium of the American Vacuum Society, Seattle, October 25-29, 1999
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Vahedi, V.1
Lin, S.2
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Tao, H.J.4
Chen, C.C.5
Tsai, C.S.6
Liang, M.S.7
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74
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(IEEE Electron Devices Society, New York)
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M. Hussein, S. Sivakumar, R. Brain, B. Beattie, P. Nguyen, and M. Fradkin, Proceedings of the International Interconnect Technology Conference (IITC) (IEEE Electron Devices Society, New York, 2002).
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Hussein, M.1
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Brain, R.3
Beattie, B.4
Nguyen, P.5
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77
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0037348018
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R. A. Gottscho, J. K. LaCara, and J. V. Tietz, Solid State Technol., 44 (2003). Most of the economic study data are presented only in the on-line version, which, on 5/19/2003, was found to be available at
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Solid State Technol.
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Gottscho, R.A.1
LaCara, J.K.2
Tietz, J.V.3
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0242705665
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note
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Modeling done with the simulation package "Extend" published by Imagine That Inc., . A discussion of this package is given by D. Krahl in Proceedings of the 2002 Winter Simulation Conference, edited by E. Yücesan, C.-H. Chen, J. L. Snowdon, and J. M. Charnes, p. 205; A discussion is also given in Simulation Modeling and Analysis, by A. Law and D. Kelton, ISBN 0070592926. Extent is detailed on pp. 219-227.
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80
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0242705666
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(Institute of Electrical Engineers of Japan)
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T. Koshizawa et al., Proceedings of the 1st International Symposium on Dry Process, Tokyo, November 20-21, 2001 (Institute of Electrical Engineers of Japan), pp. 93-98.
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Proceedings of the 1st International Symposium on Dry Process, Tokyo, November 20-21, 2001
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Koshizawa, T.1
|