A new methodology for improved tester utilization

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 916-923

  Khoche, Ajay ^a   Kapur, Rohit ^b   Armstrong, David ^a   Williams, T W ^b   Tegethoff, Mick ^a   Rivoir, Jochen ^a  

^a AGILENT TECHNOLOGIES   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; SHIFT REGISTERS; TIMING CIRCUITS;

AUTOMATIC TEST EQUIPMENTS (ATE); TESTER RETARGETABLE PATTERN TECHNOLOGY;

INTEGRATED CIRCUIT TESTING;

EID: 0035680891     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966715     Document Type: Article

References (6)

1. Reconfigurable scan chains: A novel approach to reduce test application time
2. Control strategies for chip based DFT/BIST hardware
3. Tester retargetable patterns
4. CTL the language for describing Core Based Test