A self test program design technique for embedded DSP cores

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 22, Issue 1, 2006, Pages 71-87

  Rizk, Hani ^a,b   Papachristou, Chris ^a,c   Wolff, Francis ^a  

^a Case Western Reserve University   (United States)

^b INTEL CORPORATION   (United States)

^c CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

ATPG; DSP; LSFR; Pseudorandom BIST; Self test programs

Indexed keywords

ATPG; DSP; LSFR; PSEUDORANDOM BIST; SELF TEST PROGRAMS;

ITERATIVE METHODS; KNOWLEDGE BASED SYSTEMS; MATRIX ALGEBRA; NUMERICAL METHODS; SET THEORY;

EMBEDDED SYSTEMS;

EID: 33646541327     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-006-5549-y     Document Type: Article

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