Testability analysis and ATPG on behavioral RT-level VHDL

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 753-759

  Corno, Fulvio ^a   Prinetto, Paolo ^a   Sonza Reorda, Matteo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL INTEGRATED CIRCUITS; GENETIC ALGORITHMS; MATHEMATICAL MODELS;

AUTOMATED TEST PATTERN GENERATION (ATPG);

INTEGRATED CIRCUIT TESTING;

EID: 0031386288     PISSN: 10893539     EISSN: None     Source Type: None    
DOI: 10.1109/TEST.1997.639688     Document Type: Conference Paper

References (11)

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