Test strategies for BIST at the algorithmic and register-transfer levels

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 65-70

  Ockunzzi, Kelly A ^a   Papachristou, Chris ^b  

^a IBM MICROELECTRONICS   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Built in self test; Design for test; Test synthesis

Indexed keywords

DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; RELIABILITY; VLSI CIRCUITS;

REGISTER-TRANSFER LEVELS (RTL);

BUILT-IN SELF TEST;

EID: 0034842161     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156109     Document Type: Article

References (12)

1. Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits
2. Behavioral testability insertion for datapath/controller circuits
3. Test generation for data-path logic: The F-path method
4. A BIST scheme for RTL controller-data paths based on symbolic testability analysis
5. Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
6. Enhancing high-level control-flow for improved testability
7. Hierarchical test generation based on delayed propagation
8. Channel-based behavioral test synthesis for improved module reachability
9. Test propagation through modules and circuits
10. Breaking correlation to improve testability
11. Testability enhancement for control-flow intensive behaviors
12. TAO: Regular expression based high-level testability analysis and optimization