Sub-25 nm UTB SOI SRAM cell under the influence of discrete random dopants

Solid-State Electronics

Volumn 50, Issue 4, 2006, Pages 660-667

  Samsudin, K ^a   Cheng, B ^a   Brown, A R ^a   Roy, S ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

6T SRAM; BSIMSOI; MOSFET; Random dopants; Statistical circuit simulation; UTB SOI

Indexed keywords

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ELECTROSTATICS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE; STATISTICAL METHODS;

6T SRAM; BSIMSOI; RANDOM DOPANTS; STATISTICAL CIRCUIT SIMULATION; UTB SOI;

CMOS INTEGRATED CIRCUITS;

EID: 33646533816     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.03.019     Document Type: Article

References (18)

1. Burnett D, Erington K, Subramanian C, Baker K. Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits. In: Symp VLSI Tech; 1994.
2. Mukhopadhyay S, Mahmoodi H, Roy K. Statistical design and optimization of SRAM cell for yield enhancement. In: International conference on computer aided design (ICCAD); 2004.
3. Cheng B, Roy S, Asenov A. The impact of random doping effects on CMOS SRAM cell. In: Proceeding of the 30th European solid-state circuits conference (ESSCIRC); 2004. p. 219-22.
4. Semiconductor Industry Association (SIA). International technology roadmap for semiconductors; 2003. Available from: http://public.itrs.net.
5. Doris B., Ieong M., Kanarsky T., Zhang Y., and Roy R.A. Extreme scaling with ultra-thin Si channel MOSFETs. Proc IEDM (2002), IEEE 267-270
6. Heald R, Wang P. Variability in sub-100 nm SRAM designs. In: International conference on computer aided design (ICCAD); 2004. p. 347-52.
7. Samsudin K, Cheng B, Brown AR, Roy S, Asenov A. Impact of body thickness fluctuation in nanometre scale UTB SOI MOSFETs on SRAM cell functionality. In: Sixth European conference on ultimate integration of silicon (ULIS), Bologna, Italy; 2005. p. 45-8.
8. Asenov A., Brown A.R., Davies J.H., Kaya S., and Slavcheva G. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs. IEEE Trans Electron Dev 50 9 (2003) 1837-1852
9. Asenov A., Brown A.R., Davies J.H., and Saini S. Hierarchical approach to atomistic 3-D MOSFET simulation. IEEE Trans Comput Aided Design Integr Circ Syst 18 11 (1999) 1558-1565
10. Asenov A., Kaya S., and Brown A.R. Intrinsic parameter fluctuations in decananometre MOSFETs introduced by gate line edge roughness. IEEE Trans Electron Dev 50 (2003) 1254-1260
11. Asenov A., Kaya S., and Davies J.H. Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations. IEEE Trans Electron Dev 49 1 (2002) 112-119
12. Samsudin K, Cheng B, Brown AR, Roy S, Asenov A. UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation. In: 35th European solid-state device research conference (ESSDERC); 2005. p. 553-6.
13. BSIMSOI3.1. MOSFET model user manual, University of California, Berkeley; 2003.
14. Synopsys. Aurora: parameter extraction and optimization program user manual; March 2003.
15. Mann R.W., Abadeer W.W., Breitwisch M.J., Bula O., Brown J.S., Colwill B.C., et al. Ultralow-power SRAM technology. IBM J Res Dev 47 5/6 (2003) 553-566
16. Seevinck E., List F., and Lohstroh J. Static-noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circ 22 5 (1987) 748-754
17. Stolk P., Tuinhout H., Duffy R., Augendre E., Bellefroid L.P., Bolt M.J.B., et al. CMOS device optimization for mixed-signal technologies. Tech Digest IEDM (2001) 215-218
18. Sharma A.K. Semiconductor memories: technology, testing and reliability (1997), IEEE Press