UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 553-556

  Samsudin, K ^a   Cheng, B ^a   Brown, A R ^a   Roy, S ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTROSTATIC DEVICES; MATHEMATICAL MODELS; PARAMETER ESTIMATION; STATIC RANDOM ACCESS STORAGE;

CELL STABILITY; ELECTROSTATIC INTEGRITY; INTEGRATED MEMORY APPLICATIONS; INTRINSIC PARAMETER FLUCTUATION;

MOSFET DEVICES;

EID: 33751393874     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546708     Document Type: Conference Paper

References (12)

1. J. B. Kuang, S. Ratanphanyarat, et al., "SRAM bitline circuits on PD SOI: Advantages and concerns," IEEE Journal of Solid-State Circuits, vol. 32, June 1997.
2. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, and R. A. Roy, "Extreme scaling with ultra-thin Si channel MOSFETs," in Proc. IEDM, pp. 267-270, IEEE, 2002.
3. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE Journal of SolidState Circuits, vol. 36, April 2001.
4. K. Samsudin, B. Cheng, et al, "Impact of body thickness fluctuation in nanometre scale UTB SOI MOSFETs on SRAM cell functionality," in 6th European Conference on Ultimate Integration of Silicon, (Bologna, Italy), pp. 45-48, April 2005.
5. B. Cheng, S. Roy, and A. Asenov, "The impact of random doping effects on CMOS SRAM cell," in ESSCIRC, 2004.
6. A. R. Brown, F. Adamu-Lema, and A. Asenov, "Intrinsic parameter fluctuations in nanometre scale thin-body SOI devices introduced by interface roughness," Superlattices and Microstructures, vol. 34, pp. 283-291, 2003.
7. A. Asenov, A. R. Brown, et al., "Hierarchical approach to atomistic 3-d mosfet simulation," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 18, November 1999.
8. P. G. Drennan and C. C. McAndrew, "Understanding MOSFET mismatch for analog design," IEEE Journal of Solid-State Circuits, vol. 38, March 2003.
9. P. Su, An International Standard Model for SOI Circuit Design. PhD thesis, Electrical Engineering and Computer Science, University of California, Berkeley, 2002.
10. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, October 1987.
11. P. Stolk, H. Tuinhout, et al., "CMOS device optimization for mixed-signal technologies," Tech. Digest IEDM, pp. 215-218, 2001.
12. "International Technology Roadmap for Semiconductors," 2003.