Parallel decoding architectures for low density parity check codes

Materials Research Society Symposium - Proceedings

Volumn 626, Issue , 2001, Pages

  Howland, C ^a   Blanksby, A ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); DECODING; ELECTRIC POWER UTILIZATION;

LOW DENSITY PARITY CHECK (LDPC) CODES;

PARALLEL PROCESSING SYSTEMS;

EID: 0035033830     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)