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Volumn 626, Issue , 2001, Pages
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Parallel decoding architectures for low density parity check codes
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CODES (SYMBOLS);
DECODING;
ELECTRIC POWER UTILIZATION;
LOW DENSITY PARITY CHECK (LDPC) CODES;
PARALLEL PROCESSING SYSTEMS;
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EID: 0035033830
PISSN: 02729172
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (11)
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