Parameterized macrocells with accurate delay models for core-based designs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 319-324

  Mansour, Makram M ^a   Mansour, Mohammad M ^a   Mehrotra, Amit ^a  

^a United States of America   (United States)

Author keywords

CMOS process; CMOS technology; Decoding; Delay effects; Design methodology; Libraries; Macrocell networks; Parity check codes; Predictive models; Switches

Indexed keywords

CHANNEL CODING; CMOS INTEGRATED CIRCUITS; DECODING; LIBRARIES; SWITCHES;

CMOS PROCESSS; CMOS TECHNOLOGY; DELAY EFFECTS; DESIGN METHODOLOGY; MACRO CELLS; PARITY CHECK CODES; PREDICTIVE MODELS;

DESIGN;

EID: 0141524356     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194752     Document Type: Conference Paper

References (10)

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10. Makram M. Mansour, Layout generation for deep submicron CMOS circuits, MS thesis, University of Illinois at Urbana-Champaign, 2002.