Asymmetric SEU in SOI SRAMs

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2481-2486

  McMarr, P J ^b   Nelson, M E ^c   Liu, S T ^a,d   Nelson, D ^d   Delikat, K J ^c   Gouker, P ^a,e   Tyrrell, B ^a,e   Hughes, H ^a,b  

^a IEEE

^b NAVAL RESEARCH LABORATORY   (United States)

^c UNITED STATES NAVAL ACADEMY   (United States)

^d HONEYWELL TECHNOLOGY CENTER   (United States)

^e MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Random access memories; Silicon on insulator technology; Single event upset

Indexed keywords

HEAVY IONS; NEUTRON SOURCES; NEUTRONS; PROTONS; SILICON ON INSULATOR TECHNOLOGY; UPSETTING (FORMING);

PARTIALLY DEPLETED (PD); RANDOM ACCESS MEMORIES; SILICON-ON-INSULATOR TECHNOLOGY; SINGLE EVENT UPSET;

STATIC RANDOM ACCESS STORAGE;

EID: 33144480114     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860720     Document Type: Conference Paper

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