Distortion in RF CMOS short-channel low-noise amplifiers

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 1, 2006, Pages 46-55

  Baki, Rola A ^a,b,c   Tsang, Tommy K K ^a,b   El Gamal, Mourad N ^a,b,d,e  

^a IEEE   (Canada)

^b MCGILL UNIVERSITY   (Canada)

^c Murandi Communications Inc   (Canada)

^d IEEE   (Canada)

^e Analog/digital Committee   (Canada)

Author keywords

Closed form expressions; Intermodulation distortion; RF low noise amplifier (LNA); Second order distortion (HD2); Short channel CMOS; Third order harmonic distortion (HD3); Volterra series

Indexed keywords

GATE LENGTH; INTERMODULATION DISTORTION; LOW-NOISE AMPLIFIERS (LNA);

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DISTORTION; GATES (TRANSISTOR); INTERMODULATION; MICROPROCESSOR CHIPS; SIGNAL RECEIVERS;

AMPLIFIERS (ELECTRONIC);

EID: 31044448791     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2005.860897     Document Type: Conference Paper

References (42)

1. R. Mukhopadhyay, Y. Park, P. Sen, N. Srirattana, J. Lee, C.-H. Lee, S. Nuttinck, A. Joseph, J. D. Cressler, and J. Laskar, "Reconfigurable RFIC's in Si-based technologies for a compact intelligent RF front-end," IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 81-93, Jan. 2005.
2. M. A. Copeland, S. P. Voinigescu, D. Marchesan, P. Popescu, and M. C. Maliepaard, "5-GHz SiGe HBT monolithic radio transceiver with tunable filtering," IEEE Trans. Microw. Theory Tech., vol. 48, no. 2, pp. 170-181, Feb. 2000.
3. C. Y. Wu and C. Y. Chou, "A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 519-521, Mar. 2004.
4. X. Guan and A. Hajimiri, "A 24-GHz CMOS front-end," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 368-373, Feb. 2004.
5. T. H. Lee, H. Samavati, and H. R. Rategh, "5-GHz CMOS wireless LANs," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 268-280, Jan. 2002.
6. F. Gatta, D. Manstretta, D. Rossi, and F. Svelto, "A fully integrated 0.18 μm CMOS direct conversion receiver front-end with on-chip LO for UMTS," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 15-23, Jan. 2004.
7. S. W. Yue, D. K. Ma, and J. R. Long, "A 17.1-17.3-GHz image-reject downconverter with phase-tunable lo using 3 times subharmonic injection locking," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2321-2332, Dec. 2004.
8. M. N. El-Gamal, K. H. Lee, and T. K. Tsang, "Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications," Proc. Inst. Elect. Eng. Circuits Devices Syst., pp. 355-362, Oct.-Dec. 2002.
9. T. K. Adiseno, M. Ismail, and H. Olsson, "A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1162-1168, Sep. 2002.
10. A. Tasic, W. A. Serdijin, and J. R. Long, "Optimal distribution of the RF front-end system specifications to the RF front-end circuit blocks, " in Proc. IEEE ISCAS, 2004, pp. 889-892.
11. I. M. Filanovsky, "On design of narrow-band low-noise amplifiers with inductive source degeneration," in Proc. IEEE MWSCAS, 2000, pp. 64-67.
12. A. N. Moheldin, E. Sanchez-Sinencio, and J. Silva-Martinez, "A 2. 7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1172-1181, Jul. 2003.
13. J. W. M. Rogers and C. Plett, "A 5 GHz radio front-end with automatically Q tuned notch filter," in Proc. IEEE BCTM, 2002, pp. 69-72.
14. _, "A completely integrated 1.8 volt 5 GHz tunable image reject notch filter," in Proc. IEEE RFIC Symp., 2000, pp. 75-78.
15. T. Taris, J. B. Begueret, H. Lapuyade, and Y. Deval, "A 0.9 V body effect feedback 2 GHz low-noise amplifier," in Proc. ESSCIRC, 2003, pp. 659-662.
16. J. N. Burghartz, M. Hargrove, C. S. Webster, R. A. Groves, M. Keene, K. A. Jenkins, R. Logan, and E. Nowak, "RF potential of a 0.18 μm CMOS logic device technology," IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 864-870, Apr. 2000.
17. max realized at 0.18 μm gate length in an industrial RF-CMOS technology," in IEEE IEDM Tech. Dig., 2001, pp. 10.4.1-10.4.4.
18. min @ 6 GHz for SOC," in Proc. IEEE Int. SOI Conf., 2002, pp. 153-154.
19. L. M. Franca-Neto, R. E. Bishop, and B. A. Bloechel, "64 GHz and 100 GHz VCO's in 90 nm CMOS using optimum pumping method," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 444-538.
20. S. Kang, B. Choi, and B. Kim, "Linearity analysis of CMOS for RF applications," IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 972-977, Mar. 2003.
21. B. Toole, C. Plett, and M. Cloutier, "RF circuit implications of moderate inversion enhanced linear region in MOSFETs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 319-328, Feb. 2004.
22. P. Wambacq, P. Dobrovolny, S. Donnay, M. Engels, and I. Bolsens, "Compact modeling of nonlinear distortion in analog communication circuits," in Proc. Design, Automation Test Europe Conf. Exhibit., 2000, pp. 350-354.
23. T. W. Kim, B. Kim, and K. Lee, "Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223-229, Jan. 2004.
24. R. van Langevelde, L. F. Tiemeijer, R. J. Havens, M. J. Knitel, R. F. M. Ores, P. H. Woerlee, and D. B. M. Klaassen, "RF-distortion in deep-submicron CMOS technologies," in IEEE IEDM Tech. Dig., 2000, pp. 807-810.
25. C. H. Choi, Z. Yu, and R. W. Dutton, "Impact of poly-gate depletion on MOS RF linearity," IEEE Election Device Lett., vol. 24, no. 5, pp. 330-332, May 2003.
26. C. Fager, J. C. Pedro, N. B. de Carvalho, H. Zirath, F. Fortes, and M. J. Rosario, "A comprehensive analysis of IMD behavior in RF CMOS power amplifiers," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 24-34, Jan. 2004.
27. M. T. Terrovitis and R. G. Meyer, "Intermodulation distortion in current-commutating CMOS mixers," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1461-1473, Oct. 2000.
28. C. H. Feng, F. Jonsson, M. Ismail, and H. Osson, "Analysis of nonidealities in RF CMOS amplifiers," in Proc. IEEE ICECS, 1999, pp. 137-140.
29. S. S. Islam and A. F. M. Anwar, "Nonlinear analysis of GaN MESFET's with Volterra series using large-signal models including trapping effects, " IEEE Trans. Microw, Theory Tech., vol. 50, no. 11, pp. 2474-2479, Nov. 2002.
30. W. Kim, S. Kang, K. Lee, M. Chung, J. Kang, and B. Kim, "Analysis of nonlinear behavior of power HBT's," IEEE Trans. Microw. Theory Tech., vol. 50, no. 7, pp. 1714-1722, Jul. 2002.
31. R. A. Baki, T. K. K. Tsang, and M. N. El-Gamal, "Distortion in RF CMOS short-channel low noise amplifiers," in Proc. IEEE NEWCAS, 2005, pp. 41-44.
32. P. Wambacq, G. E. Gielen, and P. R. Kinget, "High-frequency distortion analysis of analog integrated circuits," IEEE Trans. Circuits Syst. II, Exp. Briefs, no. 3, pp. 335-345, Mar. 1999.
33. R. A. Baki, M. N. El-Gamal, and C. Beainy, "Distortion analysis of high-frequency log-domain filters using Volterra series," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, no. 1, pp. 1-11, Jan. 2003.
34. A. Gothenberg and H. Tenhunen, "Performance analysis of sampling switches in voltage and frequency domains using Volterra series," in Proc. IEEE ISCAS, 2004, pp. 765-768.
35. J. Vuolevi and T. Rahkonen, "Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, pp. 994-1001, Dec. 2003.
36. K. L. Fong and R. G. Meyer, "High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages," IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 548-555, Apr. 1998.
37. C. C. Huang, H. T. Pai, and K. Y. Chen, "Analysis of microwave MESFET power amplifiers for digital wireless communications systems," IEEE Trans. Microw. Theory Tech., vol. 52, no. 4, pp. 1284-1291, Apr. 2004.
38. A. Heiskanen, J. Aikio, and T. Rahkonen, "A 5th order Volterra study of a 30 W LDMOS power amplifier," in Proc. IEEE ISCAS, 2003, pp. 616-619.
39. S. A. Mass, "FET Models for Volterra Series Analysis," Applied Wave Research Inc., El Segundo, CA, Press release, 1999.
40. V. Aparin and L. E. Larson, "Modified derivative superposition method for linearizing FET low noise amplifiers," in Proc. IEEE RFIC Symp., 2004, pp. 105-108.
41. W. Lu et al., "BSIM3v3.2.2 MOSFET Model," Univ. California, Berkeley, 1999.
42. T. K. Tsang and M. N. El-Gamal, "Gain and frequency controllable sub-IV 5.8 GHz CMOS LNA," in Proc. IEEE ISCAS, 2002, pp. 795-798.