Linearity analysis of CMOS for RF application

IEEE Transactions on Microwave Theory and Techniques

Volumn 51, Issue 3, 2003, Pages 972-977

  Kang, Sanghoon ^a   Choi, Byounggi ^a   Kim, Bumman ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

CMOS; Linearity

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; FREQUENCIES; GATES (TRANSISTOR); NUMERICAL ANALYSIS; TRANSCONDUCTANCE;

GATE LENGTH; LINEARITY ANALYSIS; TAYLOR-SERIES ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0037361403     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2003.808709     Document Type: Article

References (5)

1. P. H. Woerlee et al., "RF-CMOS performance trends," IEEE Trans. Electron Devices, vol. 48, pp. 1776-1782, Aug. 2001.
2. S. Kang, B. Choi, and B. Kim, "Linearity analysis of CMOS for RF application," in IEEE RFIC Symp. Dig., 2002, pp. 363-366.
3. C. Wang et al., "A nonlinear capacitance cancellation technique and its application to a CMOS class AB power amplifier," in IEEE RFIC Symp. Dig., 2001, pp. 39-42.
4. "TSMC 0.25 μm Mixed-signal salicide RF Spice models," TSMC Company Ltd., Taiwan, R.O.C., Sept. 2000.
5. W. Piet and S. Willy, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998.