메뉴 건너뛰기




Volumn 24, Issue 5, 2003, Pages 330-332

Impact of poly-gate depletion on MOS RF linearity

Author keywords

Distortion; Gate capacitance; Linearity; MOSFET; Polydepletion; RF; Thin oxide

Indexed keywords

CAPACITANCE; CARRIER MOBILITY; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); POLYSILICON;

EID: 0042173094     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.812549     Document Type: Article
Times cited : (18)

References (9)
  • 1
    • 0041392390 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors, 2001 Edition. Semiconductor Industry Association. [Online]
    • International Technology Roadmap for Semiconductors, 2001 Edition. Semiconductor Industry Association. [Online]. Available: http://public.itrs.net/
  • 4
    • 0028515113 scopus 로고
    • Systematic distortion analysis for MOSFET integrators with use of a new MOSFET model
    • Sep
    • G. Groenewold and W. J. Lubbers, "Systematic distortion analysis for MOSFET integrators with use of a new MOSFET model," IEEE Trans. Circuits Syst.-II, vol. 41, pp. 569-580, Sep 1994.
    • (1994) IEEE Trans. Circuits Syst.-II , vol.41 , pp. 569-580
    • Groenewold, G.1    Lubbers, W.J.2
  • 6
    • 0031270536 scopus 로고    scopus 로고
    • Effect of gate-field dependent mobility degradation on distortion analysis in MOSFET's
    • Nov
    • R. V. Langevelde and F. M. Klaassen, "Effect of gate-field dependent mobility degradation on distortion analysis in MOSFET's," IEEE Trans. Electron Devices, vol. 44, pp. 2044-2052, Nov 1997.
    • (1997) IEEE Trans. Electron Devices , vol.44 , pp. 2044-2052
    • Langevelde, R.V.1    Klaassen, F.M.2
  • 7
    • 0033315075 scopus 로고    scopus 로고
    • 70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)
    • B. Yu, Y. Wang, H. Wang, Q. Xiang, C. Riccobene, S. Talwar, and M. R. Lin, "70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)," in IEDM Tech. Dig., 1999, pp. 509-512.
    • (1999) IEDM Tech. Dig. , pp. 509-512
    • Yu, B.1    Wang, Y.2    Wang, H.3    Xiang, Q.4    Riccobene, C.5    Talwar, S.6    Lin, M.R.7
  • 8
    • 0033891847 scopus 로고    scopus 로고
    • Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's
    • Mar
    • C.-H. Choi, J.-S. Goo, Z. Yu, and R. W. Dutton, "Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's," IEEE Trans. Electron Devices, vol. 47, pp. 655-658, Mar 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , pp. 655-658
    • Choi, C.-H.1    Goo, J.-S.2    Yu, Z.3    Dutton, R.W.4
  • 9
    • 0042394513 scopus 로고    scopus 로고
    • 2D analysis of gate polydepletion in ultra short MOSFET's
    • E. Josse and T. Skotnicki, "2D analysis of gate polydepletion in ultra short MOSFET's," in Proc. ESSDERC, 2001, pp. 207-210.
    • Proc. ESSDERC, 2001 , pp. 207-210
    • Josse, E.1    Skotnicki, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.