Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

IEEE Transactions on Nanotechnology

Volumn 1, Issue 4, 2002, Pages 214-218

  Saitoh, Masumi ^a,b   Murakami, Tasuku ^b,c   Hiramoto, Toshiro ^a,b,d,e  

^a IEEE

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^c CHUO UNIVERSITY   (Japan)

^d Institute of Electrical   (Japan)

^e JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

Author keywords

Room temperature operation; Silicon single electron transistor (SET); Thermal oxidation; Thermally activated conduction; Tunneling barrier height

Indexed keywords

ROOM-TEMPERATURE OPERATION; SILICON SINGLE-ELECTRON TRANSISTOR (SET); THERMAL OXIDATION; THERMALLY ACTIVATED CONDUCTION; TUNNELING BARRIER HEIGHT;

CHEMICAL VAPOR DEPOSITION; ELECTRIC POTENTIAL; FIELD EFFECT TRANSISTORS; OXIDATION; SILICON; THERMAL CONDUCTIVITY;

ELECTRON TUNNELING;

EID: 3042814825     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2002.807379     Document Type: Conference Paper

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