Circuit-level reliability requirements for Cu metallization

IEEE Transactions on Device and Materials Reliability

Volumn 5, Issue 3, 2005, Pages 522-530

  Alam, Syed M ^a,b,c,f   Gan, Chee Lip ^a,d   Wei, Frank L ^e,f,g   Thompson, Carl V ^a,e   Troxel, Donald E ^a,b,h,i,j  

^a IEEE   (United States)

^b Department of Electrical Engineering and Computer Science   (United States)

^c FREESCALE SEMICONDUCTOR INC   (United States)

^d NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^e Massachusetts Institute of Technology   (United States)

^f Sigma Xi Scientific Research Society   (United States)

^g Materials Research Society   (United States)

^h MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

ⁱ ASSOCIATION FOR COMPUTING MACHINERY   (United States)

^j Association for Computing Machinery ^*  (United States)

more..

Author keywords

Aluminum interconnects; Barrierless via; Circuit level reliability simulation; Copper interconnects; Electromigration; Integrated circuit (IC) reliability; Reliability estimation

Indexed keywords

ALUMINUM INTERCONNECTS; BARRIERLESS VIA; CIRCUIT-LEVEL RELIABILITY SIMULATION; COPPER INTERCONNECTS; INTEGRATED-CIRCUIT (IC) RELIABILITY; RELIABILITY ESTIMATION;

ALUMINUM; DIFFUSION; ELECTROMIGRATION; FILTRATION; NETWORKS (CIRCUITS);

COPPER METALLURGY;

EID: 29344465617     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2005.853507     Document Type: Article

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