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Volumn , Issue , 2005, Pages 78-85

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

Author keywords

Buffering; Chemical Mechanical Polishing (CMP); Design for Manufacturing; Wire Sizing; Yield

Indexed keywords

CHEMICAL MECHANICAL POLISHING; ELECTRIC POWER SYSTEM INTERCONNECTION; MATHEMATICAL MODELS; OPTIMIZATION; PROBABILITY DENSITY FUNCTION;

EID: 29144516335     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055154     Document Type: Conference Paper
Times cited : (13)

References (25)
  • 1
    • 0042635808 scopus 로고    scopus 로고
    • Death, taxes and failing chips
    • Jun
    • C. Visweswariah, "Death, taxes and failing chips," in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Visweswariah, C.1
  • 2
    • 0041589397 scopus 로고    scopus 로고
    • Performance-impact limited area fill synthesis
    • Jun
    • Y. Chen, P. Gupta, and A. B. Kahng, "Performance-impact limited area fill synthesis," In DAC, Jun 2003.
    • (2003) DAC
    • Chen, Y.1    Gupta, P.2    Kahng, A.B.3
  • 4
    • 4444353564 scopus 로고    scopus 로고
    • Towards a systematic-variation aware timing methodology
    • Jun
    • P. Gupta and F. Heng, "Towards a systematic-variation aware timing methodology," in DAC 04, Jun 2004.
    • (2004) DAC 04
    • Gupta, P.1    Heng, F.2
  • 5
    • 0041633575 scopus 로고    scopus 로고
    • Statistical timing for parametric yield prediction of digital integrated circuits
    • Jun
    • J. Jess, K. Kalafala, S. Naidu, R. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Jess, J.1    Kalafala, K.2    Naidu, S.3    Otten, R.4    Visweswariah, C.5
  • 6
    • 0041633857 scopus 로고    scopus 로고
    • Computation and refinement of statistical bounds on circuit delay
    • Jun
    • A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3    Vrudhula, S.4
  • 9
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree networks for minimal Elmore delay
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 865-868, 1990.
    • (1990) Proc. IEEE Int. Symp. on Circuits and Systems , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 10
    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • Nov
    • A. Devgan and C. Kashyap, "Block-based static timing analysis with uncertainty," in ICCAD 03, Nov 2003.
    • (2003) ICCAD 03
    • Devgan, A.1    Kashyap, C.2
  • 11
    • 0346778720 scopus 로고    scopus 로고
    • Manufacturing-aware physical design
    • Oct
    • P. Gupta and A. B. Kahng, "Manufacturing-aware physical design," in ICCAD, Oct 2003.
    • (2003) ICCAD
    • Gupta, P.1    Kahng, A.B.2
  • 12
    • 25144432347 scopus 로고    scopus 로고
    • Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization
    • Mar
    • L. He, A. B. Kahng, K. Tam, and J. Xiong, "Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization," in Proc. SPIE Microlithography, Mar 2005.
    • (2005) Proc. SPIE Microlithography
    • He, L.1    Kahng, A.B.2    Tam, K.3    Xiong, J.4
  • 15
  • 23
    • 84949480508 scopus 로고    scopus 로고
    • Design sensitivities to variability: Extrapolations and assessments in nanometer vlsi
    • Sept
    • Y. Cao, P. Gupta, A. Kahng, D. Sylvester, and J. Yang, "Design sensitivities to variability: Extrapolations and assessments in nanometer vlsi," in ASIC/SOC Conference, Sept 2002.
    • (2002) ASIC/SOC Conference
    • Cao, Y.1    Gupta, P.2    Kahng, A.3    Sylvester, D.4    Yang, J.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.