Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 7, 2001, Pages 902-910

  Tian, Ruiqi ^b,c   Wong, D F ^a,b   Boone, Robert ^a,c  

^a IEEE

^b University of Texas at Austin   (United States)

^c MOTOROLA INC   (United States)

Author keywords

Chemical mechanical polishing; Design for manufacturability; Dummy features; Linear programming

Indexed keywords

ALGORITHMS; CHEMICAL MECHANICAL POLISHING; INTEGRATED CIRCUIT MANUFACTURE; LINEAR PROGRAMMING; LOGIC PROGRAMMING; VLSI CIRCUITS;

DESIGN FOR MANUFACTURABILITY; DUMMY FEATURE PLACEMENT PROBLEM;

SEMICONDUCTOR DEVICE MODELS;

EID: 0035397806     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.931037     Document Type: Article

References (10)

1. Chemical-mechanical polishing of interlayer dielectric: A review
2. Filling algorithms and analyzes for layout density control
3. Modeling of chemical-mechanical polishing: A review
4. An integrated characterization and modeling methodology for CMP dielectric planarization
5. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
6. A closed-form analytical model for ILD thickness variation in CMP processes
7. Oxide CMP mechanisms
8. A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films