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1
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28544441925
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http://www.itrs.net/Common/2004Update/2004Update.htm
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2
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0033335459
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A practical technology path to sub-0.10 micron process generations via enhanced optical lithography
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BACUS
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J. Fung Chen et al., "A Practical Technology Path to Sub-0.10 Micron Process Generations Via Enhanced Optical Lithography," SPIE Vol.3783-108, BACUS 1999.
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SPIE
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Chen, J.F.1
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3
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21144474740
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Contact and via hole mask design optimization for 65nm technology node
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BACUS
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Douglas Van Den Broeke et al., "Contact and Via Hole Mask Design Optimization for 65nm Technology Node," SPIE Vol. 5567-73, BACUS 2004.
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SPIE
, vol.5567
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Van Den Broeke, D.1
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4
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28544441001
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Manufacturing implementation for 90nm and 65nm contact and via masks using IMLô technology
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Photo Mask Japan, to be published
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Michael C. W. Hsu et al., "Manufacturing Implementation for 90nm and 65nm Contact and Via Masks Using IMLô Technology," SPIE Vol. 5853-50, Photo Mask Japan 2005, to be published.
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(2005)
SPIE
, vol.5853
, Issue.50
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Hsu, M.C.W.1
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5
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28544449868
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Exploring the final frontier in optical lithography via resolution enhancement technology masks
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Session 4, Lithography Technology, June 10
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J. Fung Chen, "Exploring the Final Frontier in Optical Lithography via Resolution Enhancement Technology Masks," Taiwan Semiconductor Fair, Session 4, Lithography Technology, June 10, 2004
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(2004)
Taiwan Semiconductor Fair
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Chen, J.F.1
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6
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0035758758
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Binary halftone chromeless PSM technology for lambda/4 optical lithography
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SPIE
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J. Fung Chen et al., "Binary Halftone Chromeless PSM Technology for Lambda/4 Optical Lithography," SPIE Vol. 4346, SPIE 2001.
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SPIE
, vol.4346
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Chen, J.F.1
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7
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18644379512
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Dipole decomposition mask-design for full chip implementation at the 100nm technology node and beyond
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Stephen D. Hsu et al, "Dipole Decomposition Mask-design for Full Chip Implementation at the 100nm Technology Node and Beyond," SPIE Vol. 4691, p476-490 2002.
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(2002)
SPIE
, vol.4691
, pp. 476-490
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Hsu, S.D.1
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8
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0141722453
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65-nm full-chip implementation using double dipole lithography
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Stephen D. Hsu et al, "65-nm full-chip implementation using double dipole lithography," SPIE Vol. 5040, 2003
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(2003)
SPIE
, vol.5040
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Hsu, S.D.1
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9
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3843083858
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Experimental verification of a model based decomposition method for double dipole lithography
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Mark Eurling et al, "Experimental verification of a model based decomposition method for Double Dipole Lithography," SPIE Vol. 5377, 2004
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(2004)
SPIE
, vol.5377
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Eurling, M.1
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11
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28544449281
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US Patent 6,808,981
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US Patent 6,808,981
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12
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28544435150
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US Patent 6,545,904
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US Patent 6,545,904
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13
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28544436761
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Feasibility study of double exposure lithography for 45nm node
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Photo Mask Japan, to be published
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Stephen D. Hsu et al., "Feasibility Study of Double Exposure Lithography for 45nm Node," SPIE Vol. 5853-114, Photo Mask Japan 2005, to be published.
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(2005)
SPIE
, vol.5853
, Issue.114
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Hsu, S.D.1
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14
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24044512842
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2 45nm node 6-transistor SRAM cell
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SPIE, to be published
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2 45nm node 6-transistor SRAM cell," SPIE Vol. 5756-12, SPIE 2005, to be published.
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(2005)
SPIE
, vol.5756
, Issue.12
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Verhaegen, S.1
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15
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28544451153
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Patent pending, ASML Mask Tools
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Patent pending, ASML Mask Tools
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16
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28544442626
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1 lithography with polarized illumination and immersion
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Photo Mask Japan, to be published
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1 Lithography with Polarized Illumination and Immersion," SPIE Vol. 5853-64, Photo Mask Japan 2005, to be published.
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(2005)
SPIE
, vol.5853
, Issue.64
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Chen, T.1
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18
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21144460468
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1
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BACUS
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1," SPIE Vol. 5567-67, BACUS 2004.
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(2004)
SPIE
, vol.5567
, Issue.67
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Shi, X.1
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19
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28544444163
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Simultaneous source mask optimization
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Photo Mask Japan, to be published
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Robert J. Socha et al., "Simultaneous Source Mask Optimization," SPIE Vol. 5853-105, Photo Mask Japan 2005, to be published.
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(2005)
SPIE
, vol.5853
, Issue.105
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Socha, R.J.1
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