Optical extensions integration for a 0.314μm2 45nm node 6-transistor SRAM cell

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5756, Issue , 2005, Pages 120-130

  Verhaegen, Staf ^a   Nackaerts, Axel ^a   Wiaux, Vincent ^a   Hendrickx, Eric ^a   Vandenberghe, Geert ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING; OPTICAL RESOLVING POWER; OPTIMIZATION; PRODUCT DESIGN; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

CONTACT HOLES; OPTICAL EXTENSIONS INTEGRATION; POLY GATES; RESOLUTION ENHANCEMENT;

PHOTOLITHOGRAPHY;

EID: 24044512842     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.600862     Document Type: Conference Paper

References (8)

1. Monique Ercken, et. al., "Challenges in Patterning 45nm Node Multiple-Gate Devices and SRAM cells", Interface 2004 (2004)
2. A. Rosenbluth, "Optimum Mask and Source Patterns to Print a Given Shape", Proc. of SPIE, vol. 4346, p. 486 (2001).
3. D. G. Flagello, et. al., "Optical lithography in the sub-50nm regime", Proc. SPIE, vol. 5377, p. 21 (2004)
4. D. J. Van Den Broeke, et. al., "Near 0.3 kl full-pitch range contact hole patterning using chromeless phase lithography (CPL)", Proc. of SPIE, vol. 5256, p. 297 (2003)
5. R. Socha, et. al., "Contact Hole Reticle Optimization by Using Interference Mapping Lithography (IMLTM)", Proc. of SPIE, vol. 5377, p. 223 (2004)
6. R. Rubingh, et. al., "Lithographic performance of a dual stage, 0.93NA ArF step and scan system", Proc. of SPIE, vol. 5754, to be published (2005)
7. 2 6T-SRAM Cell build with Tall Triple-Gate Devices for 45nm node applications using 0.75NA 193nm lithography", IEDM 2004, p.269 (2004)
8. 2 6T-SRAM Cell and Advanced CMOS Logic Circuits", Symp. On VLSI Technology 2005, to be published (2005)